View HD64413A_134018.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

To all our customers
Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Renesas Technology Home Page: http://www.renesas.com
Renesas Technology Corp. Customer Support Dept. April 1, 2003
Cautions
Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. 2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein.
SuperH RISC engine Peripheral LSI
TM
HD64413A Q2SD
Quick 2D Graphics Renderer with Synchronous DRAM Interface
User's Manual
ADE-602-204A Rev. 2.0 09/24/02 Hitachi, Ltd.
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products.
Rev. 2.0, 09/02, page ii of xviii
General Precautions on Handling of Product
1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product's state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system's operation is not guaranteed if they are accessed.
Rev. 2.0, 09/02, page iii of xviii
Configuration of This Manual
This manual comprises the following items: 1. 2. 3. 4. 5. General Precautions on Handling of Product Configuration of This Manual Preface Contents Overview
6. Description of Pins * Pin configuration * Pin Arrangement * Pin Functions 7. Description of UGM Architecture 8. Description of Display List The configuration of the functional description of each command differs according to the command. However, the generic style includes the following items: i) Function ii) Command Format iii) Command Description iv) Example 9. Descriptions of Registers * List of Registers * Descriptions of Registers 10. Usage Notes When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descriptions given, and usage notes are given. 11. Electrical Characteristics 12. Appendix
Rev. 2.0, 09/02, page iv of xviii
Preface
The Q2SD (Quick 2D Graphics Renderer with Synchronous DRAM Interface) is a 2D graphics renderer that supports SDRAM interface in the SH microcomputer graphics accelerator "Quick" series (Q Series), based on the concepts of simplicity, realtime operation, and upgradability. The Q2SD is a high-performance graphics rendering LSI for multimedia applications, which provides both drawing and display, video input functions integrated into a single chip. Target Users: This manual was written for users who will be using the Q2SD Series in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of the Q2SD Series to the target users. In this revised version, descriptions of the video input function, the list of related manuals, and points to have gotten questions from customers are reviewed.
Notes on reading this manual: * Read the manual according to the contents. This manual can be roughly categorized into parts on overview, descriptions of the UGM architecture, display list, and registers, and usage notes. These are arranged in that order. Rules: Number notation: Signal notation: Binary is Bxxxx, hexadecimal is Hxxxx. An overbar is added to a low-active signal: [[[[
Related Manuals:
The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.hitachisemiconductor.com/
Q2SD Series manuals:
Manual Title Q2SD Series Hardware Manual ADE No. This manual
Application notes:
Manual Title HD64413A Q2SD Application Notes/Q & A ADE No. ADE-502-070
Rev. 2.0, 09/02, page v of xviii
Contents
Section 1 Overview ....................................................................................... 1
1.1 1.2 1.3 1.4 Features ....................................................................................................................... 2 A List of Specifications................................................................................................ 9 Block Diagram............................................................................................................. 10 Processing States ......................................................................................................... 13 1.4.1 Power On ........................................................................................................ 13 1.4.2 Initial States (when Specified Power is Supplied)............................................. 13 1.4.3 Reset State (when Low Level is Input to 5(6(7 Pin) ...................................... 14 1.4.4 UGM Initialization State.................................................................................. 14 1.4.5 Normal Operating State ................................................................................... 14
Section 2 Pins................................................................................................ 15
2.1 2.2 2.3 2.4 Pin Configuration......................................................................................................... 15 Pin Arrangement.......................................................................................................... 16 Pin Functions............................................................................................................... 17 System Control Pins..................................................................................................... 23 2.4.1 Operating Mode Pins ....................................................................................... 23 2.4.2 Clock Pins....................................................................................................... 23 2.4.3 Reset Pin......................................................................................................... 25 2.4.4 Power Supply Pin ............................................................................................ 25 CPU Interface Pins....................................................................................................... 26 2.5.1 CPU Writes ..................................................................................................... 26 2.5.2 CPU Reads...................................................................................................... 26 2.5.3 DMA Writes.................................................................................................... 27 2.5.4 Interrupts......................................................................................................... 28 UGM Interface Pins ..................................................................................................... 28 Display Interface Pins .................................................................................................. 28 2.7.1 Display Signal Output ..................................................................................... 28 2.7.2 Video Encoder Interface .................................................................................. 29 2.7.3 CRT Interface.................................................................................................. 29 2.7.4 D/A Converter................................................................................................. 29 Video Interface Pins..................................................................................................... 30 2.8.1 Video Input Interface....................................................................................... 30
2.5
2.6 2.7
2.8
Section 3 UGM Architecture ......................................................................... 33
3.1 3.2 Features ....................................................................................................................... 33 Q2SD Access............................................................................................................... 34 3.2.1 UGM Access Priority ...................................................................................... 34 3.2.2 UGM Access by the CPU ................................................................................ 35
Rev. 2.0, 09/02, page vi of xviii
3.3
3.4
3.5
3.6
3.7
3.2.3 UGM Access by DMAC .................................................................................. 35 3.2.4 UGM Access by Q2SD.................................................................................... 35 3.2.5 Register Access from the CPU ......................................................................... 36 3.2.6 Register Updating............................................................................................ 37 3.2.7 Byte Exchange Function .................................................................................. 39 3.2.8 2-Dimensional Image Data Exchange Function ................................................ 40 3.2.9 Input Color Data Configurations ...................................................................... 44 3.2.10 Configurations of Data in UGM ....................................................................... 47 3.2.11 Q2SD Internal Data Format ............................................................................. 49 3.2.12 Interrupt Output Function ................................................................................ 50 Unified Graphics Memory (UGM)................................................................................ 51 3.3.1 Memory Address ............................................................................................. 51 3.3.2 Memory Map................................................................................................... 56 3.3.3 Coordinate Systems ......................................................................................... 59 3.3.4 Double-Buffering Control ................................................................................ 68 3.3.5 Refresh Control ............................................................................................... 74 Display ........................................................................................................................ 75 3.4.1 Display Functions............................................................................................ 75 3.4.2 Screen Display Composition ............................................................................ 78 3.4.3 Scanning Systems............................................................................................ 81 3.4.4 Synchronization Systems ................................................................................. 90 3.4.5 Color Expansion of Display Screen.................................................................. 94 Rendering .................................................................................................................... 96 3.5.1 Commands ...................................................................................................... 96 3.5.2 Image Data Reference...................................................................................... 98 3.5.3 Rendering Attributes........................................................................................ 101 3.5.4 Command Fetching.......................................................................................... 110 3.5.5 Internal Buffer................................................................................................. 113 Video Capture.............................................................................................................. 114 3.6.1 Configuring Circuit for Video Capture ............................................................. 114 3.6.2 Video Capture Mode........................................................................................ 116 3.6.3 Reduction of Video Capture Images................................................................. 122 3.6.4 Setting Video Capture Position ........................................................................ 123 3.6.5 Format of Captured Data.................................................................................. 125 3.6.6 YCbCr and RGB Data ..................................................................................... 127 Video Display Function................................................................................................ 128 3.7.1 Video Screen Display ...................................................................................... 128 3.7.2 Relationship between the Display Mode and Video-Capture Mode ................... 129
Section 4 Display List ....................................................................................137
4.1 Four-Vertex Screen Drawing........................................................................................ 138 4.1.1 POLYGON4A................................................................................................. 138 4.1.2 POLYGON4B ................................................................................................. 143
Rev. 2.0, 09/02, page vii of xviii
4.2
4.3
4.4
4.5
4.6
4.1.3 POLYGON4C................................................................................................. 147 Line Drawing............................................................................................................... 151 4.2.1 LINE............................................................................................................... 151 4.2.2 RLINE ............................................................................................................ 154 4.2.3 PLINE............................................................................................................. 156 4.2.4 RPLINE .......................................................................................................... 159 Work Screen Drawing Command ................................................................................. 162 4.3.1 FTRAP............................................................................................................ 162 4.3.2 RFTRAP ......................................................................................................... 165 4.3.3 CLRW ............................................................................................................ 168 Work Line Drawing ..................................................................................................... 170 4.4.1 LINEW ........................................................................................................... 170 4.4.2 RLINEW......................................................................................................... 173 Register Setting Commands ......................................................................................... 175 4.5.1 MOVE ............................................................................................................ 175 4.5.2 RMOVE.......................................................................................................... 177 4.5.3 LCOFS............................................................................................................ 179 4.5.4 RLCOFS ......................................................................................................... 181 4.5.5 SCLIP ............................................................................................................. 183 4.5.6 UCLIP ............................................................................................................ 185 4.5.7 WPR ............................................................................................................... 187 Sequence Control Commands....................................................................................... 189 4.6.1 JUMP.............................................................................................................. 189 4.6.2 GOSUB........................................................................................................... 191 4.6.3 RET ................................................................................................................ 194 4.6.4 NOP3 .............................................................................................................. 195 4.6.5 VBKEM.......................................................................................................... 196 4.6.6 TRAP.............................................................................................................. 197
Section 5 Registers ........................................................................................ 199
5.1 5.2 Register Map ............................................................................................................... 199 Interface Control Registers........................................................................................... 202 5.2.1 System Control Register (SYSR) ..................................................................... 203 5.2.2 Status Register (SR) ........................................................................................ 209 5.2.3 Status Register Clear Register (SRCR)............................................................. 213 5.2.4 Interrupt Enable Register (IER)........................................................................ 214 5.2.5 Memory Mode Register (MEMR).................................................................... 216 5.2.6 Display Mode Register (DSMR) ...................................................................... 218 5.2.7 Display Mode 2 Register (DSMR2) ................................................................ 222 5.2.8 Rendering Mode Register (REMR) .................................................................. 225 5.2.9 Input Data Conversion Mode Register (IEMR)................................................. 227 5.2.10 Video Incorporation Mode Register (VIMR).................................................... 230 Memory Control Registers ........................................................................................... 234
5.3
Rev. 2.0, 09/02, page viii of xviii
5.4
5.5
5.6
5.3.1 Display Size Registers (DSR) .......................................................................... 234 5.3.2 Display Address Registers (DSAR).................................................................. 235 5.3.3 Display List Start Address Registers (DLSAR)................................................. 236 5.3.4 Multi-Valued Source Area Start Address Register (SSAR) ............................... 237 5.3.5 Work Area Start Address Register (WSAR) ..................................................... 238 5.3.6 Background Start Coordinate Registers (BGSR)............................................... 239 5.3.7 Video Area Start Address Registers (VSAR).................................................... 240 5.3.8 Video Window Size Registers (VSIZER) ......................................................... 242 5.3.9 Cursor Area Start Address Register (CSAR)..................................................... 243 5.3.10 Rendering Start Address Register (RSAR) ....................................................... 244 Display Control Registers............................................................................................. 244 5.4.1 Display Window Registers (DSWR) ................................................................ 245 5.4.2 Horizontal Sync Pulse Width Register (HSWR) ............................................... 247 5.4.3 Horizontal Scan Cycle Register (HCR) ............................................................ 247 5.4.4 Vertical Start Position Register (VSPR) ........................................................... 247 5.4.5 Vertical Scan Cycle Register (VCR) ................................................................ 248 5.4.6 Display Off Output Registers (DOOR)............................................................. 249 5.4.7 Color Detection Registers (CDER)................................................................... 250 5.4.8 Equalizing Pulse Width Register (EQWR) ....................................................... 250 5.4.9 Separation Width Register (SPWR).................................................................. 251 5.4.10 Video Display Start Position Registers (VPR) .................................................. 252 5.4.11 Cursor Display Start Position Registers (CSR) ................................................. 253 5.4.12 Color Palette Registers (CP000R to CP255R)................................................... 255 Rendering Control Registers......................................................................................... 257 5.5.1 Command Status Registers (CSTR).................................................................. 257 5.5.2 Current Pointer Registers (CURR) ................................................................... 258 5.5.3 Local Offset Registers (LCOR)........................................................................ 259 5.5.4 User Clipping Area Registers (UCLR) ............................................................. 259 5.5.5 System Clipping Area Registers (SCLR).......................................................... 261 5.5.6 Return Address Registers (RTNR) ................................................................... 261 5.5.7 Color Offset Register (COLOR)....................................................................... 262 Data Transfer Control Registers.................................................................................... 263 5.6.1 DMA Transfer Start Address Registers (DMASR) ........................................... 263 5.6.2 DMA Transfer Word Count Registers (DMAWR)............................................ 264 5.6.3 Image Data Transfer Start Address Registers (ISAR)........................................ 265 5.6.4 Image Data Size Registers (IDSR) ................................................................... 266 5.6.5 Image Data Entry Register (IDER)................................................................... 267
Section 6 Usage Notes....................................................................................269
6.1 6.2 6.3 6.4 Power-On Sequence ..................................................................................................... 269 Use of 64-Mbit SDRAM (x16 Type) ............................................................................ 270 CPU Interface Unit FIFO ............................................................................................. 271 Video Fetching Start Timing ........................................................................................ 272
Rev. 2.0, 09/02, page ix of xviii
6.5 6.6
Drawing Using Linear Format Source .......................................................................... 272 SDRAM Mode Register Values for UGM Set by Q2SD ............................................... 273
Section 7 Electrical Characteristics ................................................................ 275
7.1 7.2 7.3 Absolute Maximum Ratings......................................................................................... 275 Recommended Operating Conditions ........................................................................... 275 Electrical Characteristics Test Methods ........................................................................ 276 7.3.1 Timing Testing................................................................................................ 276 7.3.2 Test Load Circuit (All Output and Input/Output Pins) ...................................... 277 Electrical Characteristics.............................................................................................. 278 7.4.1 DC Characteristics........................................................................................... 278 7.4.2 AC Characteristics........................................................................................... 280 Timing Charts.............................................................................................................. 288 7.5.1 Clocks............................................................................................................. 288 7.5.2 Reset Timing................................................................................................... 288 7.5.3 CPU Read Cycle Timing ................................................................................. 289 7.5.4 CPU Write Cycle Timing................................................................................. 290 7.5.5 DMA Write Cycle Timing (DMAC Q2SD) ................................................. 291 7.5.6 Interrupt Output Timing................................................................................... 295 7.5.7 UGM Read Cycle Timing................................................................................ 296 7.5.8 UGM Write Cycle Timing ............................................................................... 297 7.5.9 UGM Refresh Cycle Timing and Mode Register Setting Timing ...................... 298 7.5.10 Master Mode Display Timing .......................................................................... 300 7.5.11 TV Sync Mode Display Timing ....................................................................... 301 7.5.12 Video Interface Timing.................................................................................... 303
7.4
7.5
Appendix A Initial Register Values................................................................ 305 Appendix B Commands and Parameters ........................................................ 306
B.1 B.2 B.3 Relationship between Commands and Rendering Attributes.......................................... 306 Command Codes.......................................................................................................... 307 Command Parameter Specifications ............................................................................. 308
Appendix C Drawing Algorithms .................................................................. 316 Appendix D Package Dimensions .................................................................. 319 Appendix E Display Operating Clock and Screen Synthesis .......................... 320 Appendix F Example of System Configuration for SuperH............................ 325
F.1 F.2 F.3 Determination of Clock................................................................................................ 326 Setting of Software Weight .......................................................................................... 327 Special Notes on Connection........................................................................................ 328
Rev. 2.0, 09/02, page x of xviii
F.4 F.5
F.6
Initialization Procedures of Address-Mapped Register .................................................. 328 Memory Assignment .................................................................................................... 329 F.5.1 Memory Mapping of HD64413A ..................................................................... 329 F.5.2 Example of Area Placement in UGM ............................................................... 330 F.5.3 Address Seriation in UGM............................................................................... 332 Special Notes on Data Transfer to UGM....................................................................... 333
Appendix G Example of Display Control .......................................................334
G.1 G.2 G.3 G.4 Determination of Display Size...................................................................................... 334 Selection of Display Screen.......................................................................................... 335 Setting of Synchronous Signal...................................................................................... 336 Setting and Changing Register Values related to Display Control.................................. 340 G.4.1 Setting of Color Palette .................................................................................... 340 G.4.2 Switching Procedure of Synchronous Mode ..................................................... 340 Use of Cursor Display .................................................................................................. 340
G.5
Appendix H Example of Drawing Control......................................................342
H.1 H.2 H.3 Example of Starting Drawing ....................................................................................... 342 Example of Frame Change by Internal Updating........................................................... 342 Using Example of Draw Commands............................................................................. 345 H.3.1 Drawing Polygons ........................................................................................... 345 H.3.2 Drawing Optional Shapes ................................................................................ 345 H.3.3 Drawing Circles and Ellipses ........................................................................... 345 H.3.4 Drawing using Source Data.............................................................................. 345 H.3.5 Expressing 3D Space ....................................................................................... 346 Special Notes on Using Draw Commands..................................................................... 347 H.4.1 Notes on the Relationship of Local Offset and Current Pointer ......................... 347 H.4.2 Notes on Using Relative-Series Commands...................................................... 347 H.4.3 Notes on Using Source Data ............................................................................ 348 Functions to Support Drawing Processing..................................................................... 349 H.5.1 Suspension/Resumption of Drawing................................................................. 349
H.4
H.5
Appendix I Drawing Performance ..................................................................351 Appendix J Usage of Video Capture Function................................................354
J.1 Example of Video Capture Settings .............................................................................. 354 J.1.1 Example of Interlace Composite Capture ............................................................. 354 J.1.2 Example of Modifying Video Data Size ............................................................... 355 Example of Usage of Captured Data ............................................................................. 358 J.2.1 When Displaying Captured Data on Realtime Video Screen ................................. 358 J.2.2 When Handling Captured Data as Multi-Valued Source Data ............................... 358 Video Decoder ............................................................................................................. 363 J.3.1 Field Control by Video Decoder .......................................................................... 363
Rev. 2.0, 09/02, page xi of xviii
J.2
J.3
J.3.2 Video Decoder Settings ....................................................................................... 364
Appendix K Product Lineup .......................................................................... 366
Rev. 2.0, 09/02, page xii of xviii
Figures
Section 1 Overview Figure 1.1 Sample System Configuration ...................................................................................1 Figure 1.2 Reduced System Size Through Use of UGM Architecture..........................................2 Figure 1.3 Unified System Bus Interface ....................................................................................3 Figure 1.4 Double-Buffering Architecture..................................................................................4 Figure 1.5 Graphics Accelerator.................................................................................................5 Figure 1.6 Pipeline Graphics Processing ....................................................................................5 Figure 1.7 Display Composite Function .....................................................................................6 Figure 1.8 Digital Video Images ................................................................................................6 Figure 1.9 Data Flow when Using a 3D Algorithm .....................................................................7 Figure 1.10 Internal Block Diagram .........................................................................................12 Figure 1.11 State Transition Diagram.......................................................................................13 Section 2 Figure 2.1 Figure 2.2 Figure 2.3 Figure 2.4 Figure 2.5 Figure 2.6 Section 3 Figure 3.1 Figure 3.2 Figure 3.3 Figure 3.4 Figure 3.5 Figure 3.6 Pins Pin Configuration....................................................................................................15 Pin Arrangement .....................................................................................................16 Example of Circuit for Connection of Pins CAP1 and CAP2....................................24 Connections of Bypass Capacitors between Power Supplies Near the Pins ...............25 Example of Circuit for Connection of REXT, CBU, and CBL Pins ..........................30 Example of Connection of Video Input Pins ............................................................31
UGM Architecture Example of System Configuration Using UGM .......................................................34 Example of UGM Mapping onto CPU Memory Space .............................................34 Byte Exchange Diagram..........................................................................................40 Image Data Specifications.......................................................................................41 Register Setting Procedure for YUV/YUV-to-RGB Conversion.............................41 Example of Settings for Transferring 320 x 240 YUV Source Data to UGM by Means of Four DMA Operations.........................................................................42 Figure 3.7 Configuration of One Memory Unit (512 Bytes) ......................................................52 Figure 3.8 UGM Address Transitions.......................................................................................53 Figure 3.9 Correspondence between UGM Physical Addresses (Bytes) and 2-Dimensinal Virtual Addresses ...................................................................................................54 Figure 3.10 Work Address Space .............................................................................................55 Figure 3.11 Relationship between UGM Physical Addresses (Byte) and Work Addresses .........55 Figure 3.12 Sample Memory Map (Corresponding to 640 x 480 Screen Size, with 16 Bits/Pixel ) ...............................57 Figure 3.13 Relationship between 8-Bits/Pixel and 16-Bits/Pixel Memory Maps.......................58 Figure 3.14 Example of Frame Buffer FB1 Location When HDIS = 1 ......................................59 Figure 3.15 Screen Coordinates ...............................................................................................60 Figure 3.16 Rendering Coordinates ..........................................................................................62
Rev. 2.0, 09/02, page xiii of xviii
Figure 3.17 Multi-Valued Source Coordinates (LNi = 0) .......................................................... 64 Figure 3.18 Multi-Valued Source Coordinates with LNi = 1 Specified (Linear Address)........... 64 Figure 3.19 Binary Source Coordinates.................................................................................... 65 Figure 3.20 Work Coordinates ................................................................................................. 66 Figure 3.21 Operation in Auto Display Change Mode .............................................................. 69 Figure 3.22 Operation in Auto Rendering Mode....................................................................... 70 Figure 3.23 Operation in Manual Display Change Mode .......................................................... 72 Figure 3.24 Operation when Using VBKEM Command ........................................................... 73 Figure 3.25 Display Timing..................................................................................................... 75 Figure 3.26 Configuration of the Display Screen for Q2SD ...................................................... 78 Figure 3.27 Example of Background Screen Simple Scroll (WRAP = 0)................................... 80 Figure 3.28 Example of Background Screen Wraparound Scroll (WRAP = 1) .......................... 81 Figure 3.29 Examples of Raster Scan Control Display.............................................................. 82 Figure 3.30 Display by Interlace Sync Method......................................................................... 84 Figure 3.31 Display by Non-Interlace Method.......................................................................... 85 Figure 3.32 Non-Interlace Mode Display Output...................................................................... 86 Figure 3.33 Interlace Mode Display Output.............................................................................. 87 Figure 3.34 (1) Interlace Sync & Video Mode Output .............................................................. 88 Figure 3.34 (2) Interlace Sync & Video Mode Output .............................................................. 89 Figure 3.35 Signal Flow in TV Sync Mode .............................................................................. 91 Figure 3.36 Display Timing..................................................................................................... 93 Figure 3.37 &6<1& Output Waveform.................................................................................... 94 Figure 3.38 Drawing Functions................................................................................................98 Figure 3.39 Example of POLYGON4 Transfer Data Combinations .......................................... 99 Figure 3.40 Multi-Valued Source Data Configuration ............................................................ 100 Figure 3.41 Example of Kanji Font as Binary Source (TDX = 24, TDY = 24)......................... 100 Figure 3.42 Binary Work Data Configuration......................................................................... 101 Figure 3.43 Rendering Attribute Bit Arrangement .................................................................. 102 Figure 3.44 Example of Source Style Specification ................................................................ 103 Figure 3.45 Example of Clipping Specification ...................................................................... 104 Figure 3.46 Examples of Even/Odd Select Specifications....................................................... 105 Figure 3.47 Examples of Bold Line Drawing ......................................................................... 107 Figure 3.48 Example of Display List...................................................................................... 111 Figure 3.49 Example of Timing for Suspending and Resuming Background Screen Drawing.. 112 Figure 3.50 Updating of Q2SD's Internal Buffers................................................................... 113 Figure 3.51 Video Incorporation Signals................................................................................ 115 Figure 3.52 Video Capture Timing ........................................................................................ 115 Figure 3.53 Capture State ...................................................................................................... 116 Figure 3.54 Display State....................................................................................................... 116 Figure 3.55 Video Screen Area .............................................................................................. 118 Figure 3.56 Interlace Capture................................................................................................. 119 Figure 3.57 Interlace Composite Capture ............................................................................... 119 Figure 3.58 Interlace Capture (Odd Field).............................................................................. 120
Rev. 2.0, 09/02, page xiv of xviii
Figure 3.59 Figure 3.60 Figure 3.61 Figure 3.62 Figure 3.63 Figure 3.64 Figure 3.65 Figure 3.66 Figure 3.67 Figure 3.68 Figure 3.69 Figure 3.70 Figure 3.71 Figure 3.72 Figure 3.73
Interlace Capture (Even Field).............................................................................120 Interlace Video Input Field Handling Specification ..............................................121 Reducing the Size of the Captured Image.............................................................122 Incorrect Settings for the Reduction Ratios ..........................................................123 Setting up the Capture Area.................................................................................124 Example of the Settings for Capture Areas...........................................................125 The Flow of YCbCr (4:2:2) Data .........................................................................126 YCbCr (4:2:2) Data Format.................................................................................127 Conversion of YCbCr Data into RGB Format ......................................................128 The RGB Data Format (16 Bits/Pixel) .................................................................128 Position of the Video Image ................................................................................129 The Display of Data Captured in Interlace Mode and Display ..............................130 The Display of Data Captured in the Interlace Composite Mode...........................131 The Display of Data Captured in the Interlace Odd-Only Mode...........................132 The Display of Data Captured in the Interlace Even-Only Mode...........................133
Section 6 Usage Notes Figure 6.1 Power-On Sequence..............................................................................................269 Figure 6.2 Video Interface Timing .........................................................................................272 Section 7 Electrical Characteristics Figure 7.1 Basis of VOL Timing Testing .................................................................................276 Figure 7.2 Test Load Circuit ..................................................................................................277 Figure 7.3 Input Clocks..........................................................................................................288 Figure 7.4 Reset Timing ........................................................................................................288 Figure 7.5 CPU Read Cycle Timing (CPU Q2SD) with Hardware Wait .............................289 Figure 7.6 CPU Read Cycle Timing (CPU Q2SD) with Hardware Wait .............................290 Figure 7.7 (1) DMA Write Cycle Timing (Single Address, DMAC Q2SD) ........................291 Figure 7.7 (2) DMA Write Cycle Timing (Single Address, DMAC Q2SD) ........................292 Figure 7.7 (3) DMA Write Cycle Timing (Dual Address, DMAC Q2SD)...........................293 Figure 7.7 (4) DMA Write Cycle Timing (Dual Address, DMAC Q2SD)...........................294 Figure 7.8 Interrupt Output Timing ........................................................................................295 Figure 7.9 UGM Read Cycle Timing .....................................................................................296 Figure 7.10 UGM Write Cycle Timing...................................................................................297 Figure 7.11 (1) UGM Refresh Cycle Timing ..........................................................................298 Figure 7.11 (2) UGM Mode Register Setting Cycle Timing....................................................299 Figure 7.12 Master Mode Display Timing..............................................................................300 Figure 7.13 (1) TV Sync Mode Display Timing .....................................................................301 Figure 7.13 (2) TV Sync Mode Display Timing .....................................................................302 Figure 7.14 (1) Video Interface Timing..................................................................................303 Figure 7.14 (2) Video Interface Timing..................................................................................303 Appendix C Drawing Algorithms Figure C.1 Two Representations of a Straight Line on a Raster Display..................................316
Rev. 2.0, 09/02, page xv of xviii
Figure C.2 Comparison of (a) 8-Point Drawing and (b) 4-Point Drawing................................ 317 Figure C.3 Drawing Dot Determination Process in (a) 8-Point Drawing and (b) 4-Point Drawing ............................................................................................. 317 Appendix D Package Dimensions Figure D.1 Package Dimensions (FP-176).............................................................................. 319 Appendix F Example of System Configuration for SuperH Figure F.1 Example of System Configuration Overview......................................................... 326 Figure F.2 Example of Interface Timing ................................................................................ 327 Figure F.3 Example of Memory Mapping (Using SH7709) .................................................... 329 Figure F.4 UGM Memory Map.............................................................................................. 331 Figure F.5 UGM Address Transition Overview ...................................................................... 332 Appendix G Example of Display Control Figure G.1 Example of Display Timing ................................................................................. 334 Figure G.2 Example of Display Timing under Non-interlace Mode ........................................ 336 Figure G.3 Example of Display Timing under Interlace Sink & Video Mode .......................... 338 Figure G.4 Cursor Allocation................................................................................................. 341 Appendix H Example of Drawing Control Figure H.1 Display/Drawing Control Timing Chart (DBF = 0) ............................................... 344 Figure H.2 Example of Referencing and Branching................................................................ 346 Appendix I Drawing Performance Figure I.1 POLYGON4C Drawing Performance when FST = 0 (Drawing Range: 320 (H) x 240 (V))...................................................................... 351 Figure I.2 POLYGON4C Drawing Performance when FST = 1 (Drawing Range: 320 (H) x 240 (V))...................................................................... 352 Figure I.3 POLYGON4C Drawing Performance when FST = 0 (Drawing Range: 320 (H) x 240 (V))...................................................................... 353 Appendix J Usage of Video Capture Function Figure J.1 Interlace Composite Capture.................................................................................. 355 Figure J.2 Interlace Composite Capture (Horizontal and Vertical Reduction Ratios = 1/4) ...... 357 Figure J.3 Example of Video Data Usage............................................................................... 359 Figure J.4 Q2SD Video Setting Flow (1)................................................................................ 360 Figure J.5 Q2SD Video Setting Flow (2)................................................................................ 361 Figure J.6 Q2SD Video Setting Flow (3)................................................................................ 362 Figure J.7 Example of Connection of Video Capture Circuit .................................................. 363 Figure J.8 Example of Interlaced Data Output Timing for Decoder......................................... 364
Rev. 2.0, 09/02, page xvi of xviii
Tables
Section 1 Overview Table 1.1 A List of Specifications ............................................................................................9 Table 1.2 Pin States After Reset .............................................................................................14 Section 2 Pins Table 2.1 Pin Functions .........................................................................................................17 Table 2.2 Operating Mode Selection ......................................................................................23 Table 2.3 Input Clocks and Operating Frequencies .................................................................24 Section 3 Table 3.1 Table 3.2 Table 3.3 Table 3.4 Table 3.5 Table 3.6 Table 3.7 Table 3.8 Table 3.9 Table 3.10 Table 3.11 Table 3.12 UGM Architecture Registers with Internal Update Function..................................................................38 Interrupt Output Function .......................................................................................51 Setting for Number of Refreshes .............................................................................74 Sample Estimations of Number of Refresh Cycles...................................................74 Variables Defined by Display Screen ......................................................................76 Register Settings.....................................................................................................77 Background Screen Related Register Settings .........................................................80 Combinations of Q2SD Output and Monitor Input Methods ....................................85 Drawing Commands...............................................................................................96 Bold Line Drawing Settings ..............................................................................106 8-Bit Pixel Interface..........................................................................................126 Selecting Modes of Video Capture and Display for the Q2SD ...........................134
Section 4 Display List Table 4.1 Command List......................................................................................................137 Section 5 Registers Table 5.1 Registers ..............................................................................................................199 Table 5.2 Bit Configuration..................................................................................................226 Table 5.3 YUV Mode Setting...............................................................................................229 Table 5.4 Video Incorporation Reduction Ratio....................................................................233 Appendix G Table G.1 Table G.2 Table G.3 Table G.4 Example of Display Control Setting Example of Variables ((TVM1,0) = (0,0), (SCM1,0) = (0,0)) .................337 Register Setting Example ((TVM1,0) = (0,0), (SCM1,0) = (0,0)) .......................337 Setting Example of Variables ((TVM1,0) = (0,0), (SCM1,0) = (1,1)) .................339 Register Setting Example ((TVM1,0) = (0,0), (SCM1,0) = (1,1)) .......................339
Appendix H Example of Drawing Control Table H.1 Relationship of DBF and Display Screen (FG) ..................................................342
Rev. 2.0, 09/02, page xvii of xviii
Rev. 2.0, 09/02, page xviii of xviii
Section 1 Overview
The Q2SD (Quick 2D Graphics Renderer with Synchronous DRAM Interface) is a 2D graphics renderer that supports SDRAM interface in the SH microcomputer graphics accelerator "Quick" series (Q Series), based on the concepts of simplicity, realtime operation, and upgradability. The use of unified graphics memory (UGM), a double-buffering system that switches drawing and display buffers in frame units, and the video-input function, providing a high-speed drawing performance of 60 screens per second, has made possible minimization of graphics memory (with the minimum configuration of a single 16-Mbit SDRAM memory), unified handling of graphics and natural images, and realtime software 3D graphics drawing. The separation of geometric operations (handled by the CPU) and rendering operations (handled by the Q2SD) has also resulted in improved system bus utilization. The Q2SD is a high-performance graphics rendering LSI for multimedia applications, which provides both drawing and display, video input functions integrated into a single chip. A sample Q2SD system configuration is shown in figure 1.1.
Address control SuperH Data or (16) CPU Data (16)
Analog RGB Q2SD
Analog RGB Video amplifier Analog NTSC Video encoder
400 x 240, etc.
Address (14)
Data (16 or 32) Display list
Digital video data (8)
Video decoder
Display monitor
Cursor Video screen
Background screen*
Memory
Binary/multi-valued source Binary work area
External video
Frame Frame buffer 0* buffer 1*
UGM (SDRAM) Note: 16-bit/8-bit color precision
Figure 1.1 Sample System Configuration
Rev. 2.0, 09/02, page 1 of 366
1.1
Features
Simple (Optimized System Configuration): (1) Use of Unified Graphics Memory (UGM) Architecture * Unified handling of image data (unified graphics memory (UGM) architecture) Data in various formats can be stored and managed in the same unified graphics memory (see figure 1.2). * Minimum necessary UGM Minimum UGM configuration: One 16-bit-data-bus type 16-Mbit synchronous DRAM
menu
Monochrome font (binary source)
2D Quick Quick
AM
Foreground screen (double buffer)
Color (multi-valued source) 8 bits/pixel 16 bits/pixel
MS 16
DR
G
Background screen
Minimum configuration: 16-Mbit SDRAM
Monochrome pattern (binary work area) POLYGON... Display list (16-bit instructions)
Video screen
Cursor (2 pcs)
Figure 1.2 Reduced System Size Through Use of UGM Architecture
Rev. 2.0, 09/02, page 2 of 366
* Allocating the UGM in the CPU's memory space A CPU interface circuit is incorporated to provide a unified interface. The UGM is allocated in the CPU's memory space (see figure 1.3). This simplifies the UGM management by the CPU.
UGM (Unified Graphics Memory)
SDRAM
2SD
Frame buffer 0 Binary work area
Frame buffer 1
Binary/multi-valued source
Display list
The CPU can access the UGM directly via the Q2SD
Figure 1.3 Unified System Bus Interface
Rev. 2.0, 09/02, page 3 of 366
Realtime: (1) Use of Double-Buffering Architecture The use of a double-buffering architecture that allows switching between the drawing buffer and display buffer in frame or field units enables realtime operation by synchronous with display processing with high-speed drawing processing (see figure 1.4).
Drawing
Frame buffer (dispalying)
Quick Quick
2D
Frame buffer (drawing) Double-buffer control
Q Q u2 uD ic ic k k
Quick
2D
ic Qu
2Dk
Qu 2D ick
2 k Quic
D
Displaying Monitor
Quick Quick
2D
Quick
2D
2Dk ic Qu
Switching buffers
Drawing
Frame buffer (drawing)
Dk 2 ck i ic u u Q Q
Frame buffer (displaying)
Qu 2D Q iick
Double-buffer control
Q Q u2 uD ic ic k k
Monitor
Qu 2D ick
Figure 1.4 Double-Buffering Architecture
Rev. 2.0, 09/02, page 4 of 366
2D k iic Q Qu
Quick
2D
2 k Quic Q
2D Quick
D
Displaying
Q Q u2 uD ic ic k k
(2) Graphics Accelerator A Dedicated hardware is used for the inefficient processing in the CPU. Thus, CPU bus efficiency is improved and high-speed realtime drawing is realized (see figure 1.5).
Dedicated hardware is used for insufficient processing in CPU
Rendering Operation
SD 2
Control
Geometric Operation
Making display list by CPU Drawing in UGM according to display list by Q2SD CPU bus efficiency is improved by using Q2SD for all rendering processing High-speed realtime drawing
SuperH
RISC engine
Coordinates Operation
Figure 1.5 Graphics Accelerator (3) Pipeline Graphics Processing: High-speed graphics processing is enabled by pipelining the CPU geometry processing and Q2SD rendering processing (see figure 1.6).
CPU
Geometry 1 Rendering 1 Geometry 2 Rendering 2 Geometry 3 Rendering 3
CPU Q2SD
Geometry 1
Geometry 2
Geometry 3 Rendering 3
Rendering 1
Rendering 2
Processing time
Figure 1.6 Pipeline Graphics Processing (4) Use of Write-Only Drawing: Write-only drawing (a drawing method using only write operations) is used to improve drawing performance.
Rev. 2.0, 09/02, page 5 of 366
(5) Display Composite Function The drawing time can be reduced by changing only the images that have been modified (see figure 1.7).
menu
Display Cursor screen Video screen Display composite
Foreground screen
menu
Background screen
Figure 1.7 Display Composite Function (6) Digital Video Capture Realtime expression of digital video images in various types can be achieved.
(1) Full-screen display (4) Multi-screen display
Graphics display (16 bits/pixel) (RGB format) Video display 16 bits/pixel (YC format) (1) to (3): Digital video data in YCbCr 4:2:2 format is stored in the UGM with or without reduction. It is displayed on the video screen. (4): Digital video data in YCbCr 4:2:2 format is converted to the RGB565 format and is stored in the UGM. Using it as a source data, still picture is drawn in 16 bits/pixel mode.
(2) Two-screen display
(3) PinP display
P @ ,
P @ , P @ ,
8 bits/pixel
Figure 1.8 Digital Video Images
Rev. 2.0, 09/02, page 6 of 366
(7) Support for SDRAM SDRAM can be used for the UGM. This enables the Q2SD to use burst access to the UGM and perform high-speed drawing. Upgradability: (1) Algorithm Upgrading In the Q2SD's drawing system, algorithms for coordinate conversion, etc., are executed by the CPU, using a systematized data base containing coordinates and other data, and the results are represented in graphical form. Thus, the graphics for a variety of shapes can be implemented simply by upgrading the algorithms, without having to modify the data base (see figure 1.9).
Data base (coordinate vertices, etc.)
3D algorithm (software)
Drawing by Q2SD Display list
Quick Quick
2D
Quick Quick
2D
Drawn figure
Figure 1.9 Data Flow when Using a 3D Algorithm (2) Drawing System Upgrading The Q2SD has been developed as a member of the Q Series, enabling the user to select the most appropriate model from the series for a particular application. The user's drawing system can also be upgraded as necessary by changing the Q2SD or CPU combination.
Rev. 2.0, 09/02, page 7 of 366
Qu 2D ick
(3) Consistency of Application Interface The Q2SD's carefully selected drawing commands are of four kinds: four-vertex screen drawing, line drawing, work screen drawing, and work line drawing. This makes it possible to reduce the parts dependent upon drawing commands within an application, and so achieve a more consistent interface between applications.
Rev. 2.0, 09/02, page 8 of 366
1.2
A List of Specifications
Table 1.1 summarizes the specifications of the Q2SD. Table 1.1
Item Drawing Drawing performance
A List of Specifications
Function/Performance Polygon drawing performance (20 x 25 pixels): 91,000/sec (2-screen composite mode: 60,000/sec) Line drawing performance (10 pixels): 1,200,000/sec (2-screen composite mode: 400,000/sec) Color representation Drawing commands Register setting commands Sequence control commands Source: 1/8/16 bits/pixel; drawing: 8/16 bits/pixel; work: binary 4-vertex screen drawing, line drawing, work screen drawing, work line drawing Current pointer setting, local offset setting, clipping, specific address-mapped register setting Jump, subroutine, vertical blanking interval wait, no operation, display list end 320 x 240, 400 x 240, 480 x 240, 640 x 480, NTSC, PAL, etc. Non-interlace, interlace, interlace sync & video Simultaneous display of 256 colors out of 260,000 Two cursors, 32 x 32 pixels, display color selectable from color palette Foreground, background, and video screens 8-bit multiplexed YCbCr 4:2:2 digital input Drawing system internal operation maximum clock frequency (Q2SD operating frequency) 66 MHz x 1, 33 MHz x 2, 16.5 MHz x 4 (using multiplier)
Display functions
Sample screen sizes CRT scanning system Color palette Cursors Display screen
External synchronization Master, TV synchronization
Video input System
Display system internal Operating frequency/2 (max. 33 MHz) operation clock frequency (display operation clock frequency)
Rev. 2.0, 09/02, page 9 of 366
Table 1.1
Item System
Summary of Q2SD Functions (cont)
Function/Performance SH interface Command/ data transfer YUV RGB conversion YUV RGB conversion Interrupt output DMA transfer (single address, dual address), or performed by SuperH 16-bit input, 4:2:2 (8 bits each for Y, U, V) 16-bit output (R: 5, G: 6, B: 5 bits) 8-bit input (4 bits each for d-Y, d-U, d-V) 16-bit output (R: 5, G: 6, B: 5 bits) TV sync signal error flag, frame flag, DMA flag, command error flag, vertical blanking flag, trap flag, command suspend flag, drawing break flag Can be allocated to the SRAM area of the SuperH with 3.3-V power supply. Minimum 16 Mbits (choice of one 16-Mbit (x16) memory, two parallel 16-Mbit (x16) memories, one 64Mbit (x16) memory, or one 64-Mbit (x32) memory) 6-bit resolution for each of R, G, and B (8-bit resolution for each of R, G, and B for video stored in UGM in YCbCr format) 0.35- CMOS/176-pin LQFP 3.3 V 0.3 V/0C to 70C (Details of a -40C to 85C special-specification model are also available from Hitachi sales representatives)
SuperH supported UGM interface DAC 32/16-bitbus-width SDRAM Analog RGB output
Process/package Power supply voltage/temperature range
1.3
Block Diagram
Figure 1.10 shows a block diagram of the Q2SD. The functions of the various blocks in figure 1.10 are as follows. * CPU interface unit Performs UGM access by the CPU, Q2SD on-chip register accesses by the CPU, and UGM write access by the external DMAC. Converts input data YUV (260,000 colors) or YUV (260,000 colors) to RGB data (60,000 colors), and stores it in the UGM. Interrupts are output. * UGM interface unit Controls the connection relating to the SDRAM that is used for the UGM. * Chip manager Controls the operation of each unit in the UGM architecture.
Rev. 2.0, 09/02, page 10 of 366
* Clock generator (CPG0, CPG1) The Q2SD operating clock is generated in the CPG0, and it is provided to each unit excluding the display unit. The display dot clock is generated in the CPG1 and it is provided to the display unit. * Rendering unit Performs fetching and interpretation of the display list in the UGM. * Rendering buffer unit Buffers data and addresses between the rendering unit and the UGM to improve the efficiency to the UGM access in the rendering unit. * Display unit Generates the CRT control signals and outputs analog RGB signals. * Display buffer unit Composes the foreground, background, video and cursor screens. Accesses data to be displayed in synchronization with the display timing. By the color palette (6 bits per color), converts 8-bits/pixel data to display data of 256 colors out of 262,144 to the RGB data, based on the color conversion table, and when the video screen data is the YCbCr data, it is converted to the RGB data. * Video-in unit Fetches 4:2:2 YCbCr data and stores it in the UGM in YCbCr or RGB format. The image data can also be stored with reduction.
Rev. 2.0, 09/02, page 11 of 366
CLK0
CLK1
CPG0
CPG1 Display unit
I/O buffer I/O buffer
Rendering unit
DAC
I/O buffer
Video-in unit Color palette Rendering buffer unit Display buffer unit
CPU data bus
I/O buffer
CPU address bus UGM data bus UGM address bus
DMA control
YUV RGB conversion YUV RGB conversion
Chip manager
UGM interface unit
CPU interface unit
Figure 1.10 Internal Block Diagram
Rev. 2.0, 09/02, page 12 of 366
1.4
Processing States
The Q2SD has five main processing states: the power-on state, initial state, reset state, UGM initialization state, and normal states. Figure 1.11 shows the state transitions.
Power-on
Initial state
(Reset) = low
Reset state (Reset) = low (Reset release) MODE 2 to 0 = B'000, B'001, B'010 = high Normal state
(Reset) = low
UGM initialization state
Figure 1.11 State Transition Diagram 1.4.1 Power On
For details, refer to section 6.1, Power-On Sequence. 1.4.2 Initial States (when Specified Power is Supplied)
Initial states are undefined. Registers: Undefined I/O pins: Undefined Output pins: Low/high-level output
Rev. 2.0, 09/02, page 13 of 366
1.4.3
Reset State (when Low Level is Input to #$% Pin)
Table 1.2 shows the Q2SD pin states immediately after a reset. UGM refreshing is not performed when the #$% pin is low. The levels of pins MODE2 to MODE0 are latched at the rising edge of the #$% pin. At this time, they must be fixed at a level of B000, B001, or B010. Other levels must not be used because those setting makes the Q2SD enter in test mode. Table 1.2
I/O Pins
Pin States After Reset
Input state Output state (low-level output) D0 to D15*, 96<1&/(;96<1&, +6<1&/ (;+6<1&, 2'') MD0 to MD31 DISP, CDE
Output Pins
Low-level output High-level output Low/high-level output
'5(4, ,5/, :$,7 &6<1&, MA0 to MA13, 0:(, 05$6, 0&$6,
LDQM0, LDQM1, UDQM0, UDQM1, MCLK
Note: Pins D0 to D15 are in the output state when 5' is a low-level input.
1.4.4
UGM Initialization State
Initializes the SDRAM which is used for the UGM. For details on initialization, refer to section 6.6, SDRAM Mode Register Values for UGM Set by Q2SD. 1.4.5 Normal Operating State
In the normal operating state, the Q2SD executes drawing commands and performs display control.
Rev. 2.0, 09/02, page 14 of 366
Section 2 Pins
2.1 Pin Configuration
Figure 2.1 shows an overview of the Q2SD's pins. Unused input pins should be made inactive by pulling them up or down.
MODE0 to MODE2 System control (8) CLK0 CLK1 CAP1 CAP2 A1 to A22 D0 to D15 CPU interface (47)
3
CBU CBL REXT / / Display interface (12)
22 16
3
R,G,B DISP CDE VIN0 to VIN7
8
Q2SD (LQFP176)
14 32
VQCLK MA0 to MA13 MD0 to MD31
Video input interface (12)
PLLVCC Power supply (42) PLLGND DACVCC DACGND VCC GND
3 3 15 19
LDQM0 LDQM1 UDQM0 UDQM1 (also functions as MA13) MCLK Signals: Q2SD pin arrangement Capacitance: Reference: Power supply: 129 pins 4 pins 1 pin 42 pins
UGM interface (54)
Power supplies for Q2SD buffers are divided into the following groups. Power supply group 1: For PLL (2) Power supply group 2: For DAC (6) Power supply group 3: General-purpose (34)
Figure 2.1 Pin Configuration
Rev. 2.0, 09/02, page 15 of 366
2.2
Pin Arrangement
Figure 2.2 shows the pin arrangement of the Q2SD.
VIN7 VIN6 VIN5 VIN4 VIN3 VIN2 VIN1 VIN0 MD31 MD30 MD29 MD28 GND MD27 VCC MD26 MD25 GND MD24 MD16 MD17 GND MD18 VCC MD19 MD20 MD21 MD22 MD23 MA0 GND MA1 VCC MA2 MA3 NC 133 134 135 136 VQCLK 137 CLK1 138 VCC 139 / 140 GND 141 / 142 DACGND 143 DACVCC 144 R 145 G 146 DACVCC 147 B 148 DACGND 149 CBU 150 CBL 151 REXT 152 DACVCC 153 DACGND 154 155 GND 156 157 VCC 158 DISP 159 GND 160 CDE 161 162 163 164 165 166 167 168 169 VCC 170 171 GND 172 D0 173 D1 174 D2 175 D3 176 MA4 MA5 GND MA6 VCC MA7 MA8 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45
132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89
MA9 MA10 MA11 MA12 GND UDQM1/MA13 VCC UDQM0 LDQM1 LDQM0 MD8 GND MMD9 VCC MD10 MD11 MD12 MD13 MD14 MD15 GND MD7 VCC MD6 MD5 GND MD4 MD3 GND MD2 VCC MD1 MD0 PLLGND CAP2 CAP1 PLLVCC MCLK CLK0 MODE2 MODE1 MODE0
LQFP 176 (Top View)
Rev. 2.0, 09/02, page 16 of 366
D4 D5 VCC D6 GND D7 D8 D9 D10 D11 D12 VCC D13 GND D14 D15 GND A1 A2 A3 A4 A5 A6 A7 VCC A8 GND A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 VCC A19 GND A20 A21 A22
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
Figure 2.2 Pin Arrangement
2.3
Pin Functions
Table 2.1 shows the Q2SD pin functions. Table 2.1
Type System control
Pin Functions
Symbol MODE0 MODE1 MODE2 CLK0 CLK1 Pin No. 45 46 47 48 138 44 51 52 18 19 20 21 22 23 24 26 28 29 30 31 32 33 34 35 36 37 39 41 I/O Input Input Input Input Input Input Output Output Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Function Operating mode pin 0 Operating mode pin 1 Operating mode pin 2 Q2SD operating clock Display operating clock Reset Multiplication circuit external capacitance pin Multiplication circuit external capacitance pin CPU address 1 CPU address 2 CPU address 3 CPU address 4 CPU address 5 CPU address 6 CPU address 7 CPU address 8 CPU address 9 CPU address 10 CPU address 11 CPU address 12 CPU address 13 CPU address 14 CPU address 15 CPU address 16 CPU address 17 CPU address 18 CPU address 19 CPU address 20
5(6(7
CAP1 CAP2 CPU interface A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20
Rev. 2.0, 09/02, page 17 of 366
Table 2.1
Type
Pin Functions (cont)
Symbol A21 A22 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 Pin No. 42 43 173 174 175 176 1 2 4 6 7 8 9 10 11 13 15 16 162 163 164 165 166 167 168 169 171 150 151 152 145 I/O Input Input I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Input Input Input Input Input Input Output Output Output Output Output Output Output Function CPU address 21 CPU address 22 CPU data 0 CPU data 1 CPU data 2 CPU data 3 CPU data 4 CPU data 5 CPU data 6 CPU data 7 CPU data 8 CPU data 9 CPU data 10 CPU data 11 CPU data 12 CPU data 13 CPU data 14 CPU data 15 Chip select 0 (UGM) Chip select 1 (internal registers) Read strobe Write pulse 0 (lower) Write pulse 1 (upper) DMA acknowledge DMA request CPU wait Interrupt request DAC external capacitance pin DAC external capacitance pin DAC external reference pin Display data analog output R
CPU interface
&6 &6 5' :( :( '$&. '5(4 :$,7 ,5/
Display interface CBU CBL REXT R
Rev. 2.0, 09/02, page 18 of 366
Table 2.1
Type
Pin Functions (cont)
Symbol B Pin No. 146 148 157 I/O Output Output Output I/O I/O Output Output I/O Input Input Input Input Input Input Input Input Input Input Input Input Output Output Output Output Output Output Output Output Function Display data analog output G Display data analog output B Composite sync output signal Horizontal sync output/external horizontal sync input Vertical sync output/external vertical sync input Signal indicating display period (high during display period) Color detection (high in case of specific color output) Signal indicating odd field (low when odd) Video input data 0 Video input data 1 Video input data 2 Video input data 3 Video input data 4 Video input data 5 Video input data 6 Video input data 7 Video horizontal sync input Video vertical sync input Signal indicating video input odd field Video input valid data capture clock Memory address 0 Memory address 1 Memory address 2 Memory address 3 Memory address 4 Memory address 5 Memory address 6 Memory address 7
Display interface G
&6<1&
+6<1&/ 140 (;+6<1& 96<1&/ 142 (;96<1&
DISP CDE 159 161 155 125 126 127 128 129 130 131 132 134 135 136 137 103 101 99 98 95 94 92 90
2'')
Video input interface VIN0 VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN7
9+6 996 92''
VQCLK UGM interface MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7
Rev. 2.0, 09/02, page 19 of 366
Table 2.1
Type
Pin Functions (cont)
Symbol MA8 MA9 MA10 MA11 MA12 MA13 MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD15 MD16 MD17 MD18 MD19 MD20 MD21 MD22 MD23 MD24 Pin No. 89 88 87 86 85 83 54 55 57 59 60 62 63 65 76 74 72 71 70 69 68 67 113 112 110 108 107 106 105 104 114 I/O Output Output Output Output Output Output I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Function Memory address 8 Memory address 9 Memory address 10 Memory address 11 Memory address 12 Memory address 13 (also functions as UDQM1) Memory data 0 Memory data 1 Memory data 2 Memory data 3 Memory data 4 Memory data 5 Memory data 6 Memory data 7 Memory data 8 Memory data 9 Memory data 10 Memory data 11 Memory data 12 Memory data 13 Memory data 14 Memory data 15 Memory data 16 Memory data 17 Memory data 18 Memory data 19 Memory data 20 Memory data 21 Memory data 22 Memory data 23 Memory data 24
UGM interface
Rev. 2.0, 09/02, page 20 of 366
Table 2.1
Type
Pin Functions (cont)
Symbol MD25 MD26 MD27 MD28 MD29 MD30 MD31 Pin No. 116 117 119 121 122 123 124 77 78 96 97 79 80 81 83 49 3 12 25 38 56 64 73 82 91 100 109 118 139 158 170 I/O I/O I/O I/O I/O I/O I/O I/O Output Output Output Output Output Output Output Output Output Function Memory data 25 Memory data 26 Memory data 27 Memory data 28 Memory data 29 Memory data 30 Memory data 31 Memory chip select Memory write pulse Row select signal Column select signal Lower word, lower byte I/O mask Lower word, upper byte I/O mask Upper word, lower byte I/O mask Upper word, upper byte I/O mask (also functions as MA13) Memory clock
UGM interface
0&6 0:( 05$6 0&$6
LDQM0 LDQM1 UDQM0 UDQM1 MCLK Power supply VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
Power supply Buffer/internal VDD Power supply Buffer/internal VDD Power supply Buffer/internal VDD Power supply Buffer/internal VDD Power supply Buffer/internal VDD Power supply Buffer/internal VDD Power supply Buffer/internal VDD Power supply Buffer/internal VDD Power supply Buffer/internal VDD Power supply Buffer/internal VDD Power supply Buffer/internal VDD Power supply Buffer/internal VDD Power supply Buffer/internal VDD Power supply Buffer/internal VDD Power supply Buffer/internal VDD
Rev. 2.0, 09/02, page 21 of 366
Table 2.1
Type
Pin Functions (cont)
Symbol GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND PLL VCC Pin No. 5 14 27 40 58 66 75 84 93 102 111 120 141 160 172 17 61 115 156 50 I/O Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Function Buffer VSS Buffer VSS Buffer VSS Buffer VSS Buffer VSS Buffer VSS Buffer VSS Buffer VSS Buffer VSS Buffer VSS Buffer VSS Buffer VSS Buffer VSS Buffer VSS Buffer VSS Internal VSS Internal VSS Internal VSS Internal VSS Multiplication circuit VSS
Power supply
Power supply Multiplication circuit VDD Power supply DAC VDD Power supply DAC VDD Power supply DAC VDD Ground Ground Ground DAC VSS DAC VSS DAC VSS No-connection (should be open.)
PLL GND 53 DAC VCC 144 DAC VCC 147 DAC VCC 153 DAC GND 143 DAC GND 149 DAC GND 154 Other NC 133
Rev. 2.0, 09/02, page 22 of 366
2.4
2.4.1
System Control Pins
Operating Mode Pins
* MODE0, MODE1, and MODE2 These pins control the Q2SD's operating mode. The mode is fixed in a reset-startup and cannot be changed after reset. Table 2.2
MODE2 L
Operating Mode Selection
MODE1 L MODE0 L Description Normal operation state. Multiplication on. The external input clock is duty-free. The internal operating clock has the same frequency as the external input clock.
L
L
H
Normal operation state. Multiplication on. The external input clock is duty-free. The internal operating clock has twice the frequency of the external input clock.
L
H
L
Normal operation state. Multiplication on. The external input clock is duty-free. The internal operating clock has four times the frequency of the external input clock.
L H Legend
H *
H *
Setting prohibited. Setting prohibited.
H: High level L: Low level *: Either high or low level
2.4.2
Clock Pins
* CLK0, CLK 1, CAP1, and CAP2 There are two Q2SD clocks, CLK0 and CLK1. The clock used as the base for the Q2SD operating clock is input to the CLK0 pin, and the clock used as the display operating clock is input to the CLK1 pin. The Q2SD operating clock is the base clock for Q2SD's operations, and is also used as the base clock for UGM access. The Q2SD includes an operating clock multiplication circuit that enables a x1, x1/2, or x1/4 multiple of the operating clock to be selected for input to the CLK0 pin.
Rev. 2.0, 09/02, page 23 of 366
The display operating clock is the base clock for display operations, and is used to control display dot clock, display data output and generate horizontal and vertical sync signals. The relationship between the clocks and operating frequencies is summarized in table 2.3. Table 2.3 Input Clocks and Operating Frequencies
Clock Type One of the clocks on the right is the Q2SD operating clock. Input Clock Clock with the CLK0 frequency, and duty cycle adjusted to 50% Clock with twice the CLK0 frequency, and duty cycle adjusted to 50% Clock with four times the CLK0 frequency, and duty cycle adjusted to 50% CLK1 The clock on the right is the display Clock with the CLK1 frequency operating clock.
Clock Input Pin CLK0
The Q2SD operating clock and display operating clock frequencies can be set to any values within the following range. This enables to perform drawing at a maximum operating clock independently of the characteristics of the display device. Q2SD operating clock 2 x display operating clock (where display operating clock 33 MHz) CAP1 and CAP2 are external capacitance pins for the multiplication circuit. Figure 2.3 shows an example circuit for connection of pins CAP1 and CAP2. The capacitor C0 and resistor R0 of the internal PLL for oscillation settling must be placed near pins CAP1 and CAP2, and must not cross with other signals. The C0 ground must be provided from the PLLGND. C0 and R0 are an external capacitor and a noise-reduction resistor for a PLL charge pump.
R0 = about 30 PLLVCC CAP2 Q2SD CAP1 PLLGND R0 = about 30 R0 = about 0 to 2 k R0 = about 0 to 2 k C0 = about 470 pF C0 = about 470 pF System power supply
CPB = about 0.1 F
System ground
Figure 2.3 Example of Circuit for Connection of Pins CAP1 and CAP2
Rev. 2.0, 09/02, page 24 of 366
2.4.3
Reset Pin
* #$% A hardware reset signal is input to this pin. When the signal is at a low level, the Q2SD enters the hardware reset state. At this time, pin states are initialized as shown in table 1.2 and register contents are also initialized. 2.4.4 Power Supply Pin
* VCC, GND, PLLVCC, PLLGND, DACVCC, DACGND The normal power supply, DAC power supply, and PLL power supply are connected to 3.3 V. There are several normal power supply and DAC power supply pins and power must be supplied to all those pins. Normal power supply (VCC, GND), PLL power supply (PLLVCC, PLLGND), and DAC power supply (DACVCC, DACGND) must be separated from the board's power supply source, and bypass capacitors CPB, CB1, and CB2 must be inserted near the pins. Since the DAC outputs signals with high resolution, external noise should be reduced. It is recommended that at least one electrolytic capacitor should be placed each of between power supply and GND pins other than capacitors CPB, CB1, and CB2. It is also recommended that differences of voltage levels for each power supply pin should be reduced to avoid DAC's latchup and an inductance with about 100 H or a noise filter should be inserted between the DACVCC and VCC pins to cut out high frequency noise.
Rp PLLVCC PLLGND DACVCC CB1 DACGND VCC GND CB2 CB2 H CB1 System power supply CPB CPB
CPB, CB1, CB2: Capacitance about 2200 pF (lamination ceramic) C: Capacitance about 10 F (electrolytic capacitor) Rp: Resistance about 30 H: Inductance about 100 H (or noise filter)
Figure 2.4 Connections of Bypass Capacitors between Power Supplies Near the Pins
Rev. 2.0, 09/02, page 25 of 366
2.5
*
CPU Interface Pins
A1 to A22, D0 to D15, &6, &6, 5', :(, :(, '$&., '5(4, :$,7, ,5/ CPU Writes
2.5.1
The CPU can access the UGM or a Q2SD internal registers. In a UGM access, a low-level signal is input to &6; in a Q2SD internal register access, a low-level signal is input to &6. &6 and &6 must not be driven low at the same time. The UGM or Q2SD internal register address is input to A1 to A22. Input the addresses of the UGM within the range specified by the memory mode register (MEMR) to pins A1 to A22. Route the wire so that pins A22 and A21 are fixed at low levels when a single memory of 16 Mbits is in use and route the wire so that pin A22 is fixed at a low level when two memories of 16 Mbits are in use. The address is a byte address. Only word (2-byte) access can be used in the Q2SD for registers, while word access or byte access can be used for the UGM. In word access, input a low-level signal to both :( and :(; in byte access, drive :( low for an access to bits 7 to 0, or drive :( low for an access to bits 15 to 8. The Q2SD uses the :$,7 signal to notify the CPU of a delay in CPU access due to an internal Q2SD operation. However, because of the high-level width specification for the :( and :( signals, the CPU external bus operating frequency should be set equal to or lower than the Q2SD's internal operating frequency. Following detection of a low level of &6 or &6 and a low level of 5', :(, or :(, there is a maximum interval of 3 cycles, followed by an output buffer delay (max. 15 ns), before the Q2SD's :$,7 signal is asserted. The number of software waits should be adjusted by software according to the frequency ratio between the CPU and Q2SD, and system specifications such as synchronous or asynchronous operation. In some SuperH RISC engine family products, the &6 pin is initially set as an input port. If this signal is connected directly to the &6 or &6 signal of the Q2SD, pull up the SuperH's &6 pin externally to prevent the voltage level from becoming unstable in a reset. When using a CPU that uses an 5'< signal for interfacing, invert the Q2SD's :$,7 signal and use it as the 5'< signal. The :$,7 signal is output for a minimum of 1 tcyc0 when accessing the Q2SD. 2.5.2 CPU Reads
A read operation is basically the same as a write operation. Reads are performed in word units. Although write operations are indicated by signals :( and :(, read operations are indicated by the low level of the 5' signal.
Rev. 2.0, 09/02, page 26 of 366
2.5.3
DMA Writes
The CPU can perform write DMA access, using cycle stealing, to the UGM or a Q2SD addressmapped register (the image data entry register (IDE)). To perform DMA access, DMA transfer start address, DMA transfer word count, and system control register DMA mode and DMA address mode settings must be made. After the DMA mode settings are made, the Q2SD dives the '5(4 signal low as soon as its preparations are completed. When the DMA controller receives this signal, it drives the '$&. signal low and begins DMA access. DMA access is performed in word units. Use a DMA mode setting of B01 (DMA transfer to the UGM) when performing DMA writes with a YUV mode (YUV2, YUV1, YUV0 in the input data conversion mode register (IEMR)) setting of B000, and a DMA mode setting of B11 (DMA transfer to the image data entry register (IDER)) when performing DMA writes with a YUV mode setting other than B000. When DMA address mode bits DAA1 and DAA0 in the system control register (SYSR) are is set to B00 or B01, transfer is performed using single address transfer timing. When the DMA address mode (DAA1, DAA0) is set to B10, transfer is performed using dual address transfer timing. In this case, access to the Q2SD should be performed by driving '$&. low. &6 is ignored. The DMA mode is set to B01 for UGM access, and to B11 for Q2SD address-mapped register (image data entry register (IDE)) access. Other address-mapped registers cannot be accessed. The destination address (UGM address) is set as the DMA transfer start address (DMSARH, DMSARL), and the number of words set as the DMA transfer word count (DMAWRH, DMAWRL) are transferred. The Q2SD controls the UGM addresses using the on-chip address counter. Addresses input from off-chip are not used. When making another DMA mode setting after DMA transfer ends, first check that the DMF bit is set to 1 in the status register. In DMA transfer from synchronous DRAM to the Q2SD, the D0 to D15 setup time (tWRDRS) relative to the rise of the 5' signal must be at least two Q2SD system operating clock cycles, and therefore the external bus operating frequency must be no higher than 1/2 the system operating clock frequency. When using the DMAC, make the following DMAC settings. * For DMA transfer in dual address mode '$&. output in write cycle Active-low '$&. output Fixed destination address (set any UGM address) Source address incremented External request, dual address mode '5(4 falling-edge detection
Rev. 2.0, 09/02, page 27 of 366
Cycle stealing * For DMA transfer in single address mode '$&. output in read cycle Active-low '$&. output Fixed destination address Source address incremented External request, single address mode '5(4 falling-edge detection Cycle stealing The SuperH family includes models in which the initial DACK pin setting is active-high. In this case, leave the DACK pin at its initial setting (active-high) and use an external circuit to invert the DACK pin signal before connection to the Q2SD's '$&. pin. 2.5.4 Interrupts
The Q2SD requests interrupts to the CPU by means of internal sources. Interrupt sources are set in the interrupt enable register (IER).
2.6
*
UGM Interface Pins
MA0 to MA13, MD0 to MD31, 0&6, 0:(, 05$6, 0&$6, LDQM0, LDQM1, UDQM0, UDQM1, MCLK The Q2SD allows synchronous DRAM to be used as the UGM, and has a direct interface for synchronous DRAM. When connecting only one synchronous DRAM with a data bit width of 16, use pins MD0 to MD15, and leave pins MD16 to MD31 open. The operating mode of the synchronous DRAM (write mode, &$6 latency, burst type, and burst length) is set automatically by the Q2SD. For refreshing, auto-refresh mode is used. Synchronous DRAM precharging is carried out using the Precharge All Banks (PALL) command.
2.7
Display Interface Pins
The signals output from the display interface pins are all synchronized with the display operating clock. 2.7.1 Display Signal Output
* R, G, B RGB analog display signals are output. The pixel data resolution is 6 bits for each of R, G, and B. Outside the display period, the image data (R, G, B) goes to the level corresponding to H000.
Rev. 2.0, 09/02, page 28 of 366
2.7.2
Video Encoder Interface
* CSYNC Outputs the composite sync signal (&6<1&). In master mode, equalizing pulses can also be added to the composite sync signal. 2.7.3 CRT Interface
* HSYNC/(;+6<1&, 96<1&/(;96<1&, DISP, CDE, 2'') Inputs/outputs the horizontal and vertical sync signals to the HSYNC/(;+6<1& and 96<1&/(;96<1& pins. Inputs/outputs the signal indicating whether the current field is odd or even for interlace control to the 2'') pin. When the Q2SD has a mastership for synchronization, these signals are outputs. When an external device (TV or VCR) has a mastership, these signals are inputs. Since these signals are input during the reset state, they must be pulled up to fix the levels, meaning that the direction is a non-significant. The TV sync mode bits in the display mode register (bits TVM1 and TVM0 in DSMR) select either master (output) or TV sync (input). The CDE pin outputs a high level when a specified color in a display area in the UGM is detected. CDER specifies the color to be detected. Display synthesis of external video and Q2 graphics image in one pixel units is enabled by using the CDE pin for selecting the external selection circuit for the external video or Q2 graphics image. The DISP signal indicates the display period in which the high level is output. 2.7.4 D/A Converter
* CBU, CBL, and REXT The D/A converter changes output levels linearly in accordance with the display data. Connect the specified resistors or capacitors to the REXT, CBU, and CBL pins. Connect resistive load RL to the R, G, and B output pins. The relationship between Ioutmax which is the maximum value of the output current Iout and REXT can be given in the following expression. REXT = (2.842/Iout) x DACVCC. Where Vout is an amplitude when the current of Ioutmax is flowing in the resistive load RL, REXT can given in the following expression. REXT = (2.842/(Vout/RL)) x DACVCC Therefore, to obtain Vout = 1 Vpp when RL = 330 and DACVCC = 3.3 V, REXT = 3.1 k. The range of maximum output current Ioutmax must be set within the range from 2.0 mA to 3.0 mA.
Rev. 2.0, 09/02, page 29 of 366
The D/A converter has 8-bit resolution, but the dynamic settling error is determined by resistive load RL, output pin load C (total of routing and video amp input capacitances), and display operating frequency f. For example, when RL = 330 , C = 20 pF, and f = 33 MHz, the value of n when the following equation is satisfied is the D/A converter accuracy.
exp
( RL-1C f )
1 2n
(Where n is an integer)
Since n is 6 in this case, the D/A converter has 6-bit accuracy. (The dynamic settling error is 6 1/2 = 1.56% full-scale.)
Q2SD DACVCC CBU 0.1 F CBL REXT DACGND R IOUT G IOUT B IOUT RL = 330 RL = 330 RL = 330 3.1 k
+ -
0.1 F
Power supply
Ground 75
+ -
75
Analog RGB output
+ -
75
Video amp
Figure 2.5 Example of Circuit for Connection of REXT, CBU, and CBL Pins
2.8
*
Video Interface Pins
VIN0 to VIN7, 9+6, 996, 92'', VQCLK Video Input Interface
2.8.1
An 8-bit YCbCr 4:2:2 video data that is synchronous with the VQCLK must be input to VIN0 to VIN7. Input must be made to the VQCLK only when there is a valid data in data pairs. A horizontal and vertical synchronous signals must be input to 9+6 and 996. The start position of
Rev. 2.0, 09/02, page 30 of 366
the data fetching is determined by these signals. A signal indicating the video input field must be input to 92''. A low-level signal indicates the odd field and a high-level signal indicates the even field.
Q2SD VHS VVS VODD VQCLK VIN7 to VIN0 NTSC Video decoder 10 F VSYNC HSYNC FIELD VCLK VDATA7 to VDATA0 YIN 75
NTSC Vin
CLK Sample clock 28.6363 MHz
Figure 2.6 Example of Connection of Video Input Pins
Rev. 2.0, 09/02, page 31 of 366
Rev. 2.0, 09/02, page 32 of 366
Section 3 UGM Architecture
3.1 Features
The unified graphics memory (UGM) connected to the Q2SD is used for the following purposes. * Foreground (FG), background (BG), and cursor screen areas Areas that perform drawing and displaying. Double-buffering architecture (Frame buffer 0: FB0, frame buffer 1: FB1) is used for the foreground screens. Display list area Area that stores the Q2SD command list. The Q2SD fetches commands from this area while carrying out drawing operations. Work, Source, and rendering areas, Used as the work area that stores patterns for painting or cutting-out and is for drawing with FTRAP command, as the binary source area that stores font data, as the multi-valued source area that stores natural images and icons, and as the rendering area that is specified by RSAR. Video area Stores video data for three screens taken by the video capture function (the size of a single screen is a video-window size). Others The UGM can be allocated to part of the CPU's main memory area, enabling it to be used as CPU work areas as well as for the above purposes.
*
*
*
*
Figure 3.1 shows a sample system configuration using the UGM, and figure 3.2 shows an example of UGM mapping onto the CPU memory space.
Rev. 2.0, 09/02, page 33 of 366
CPU CPU bus
Main memory
Q2SD
Display data
UGM
Figure 3.1 Example of System Configuration Using UGM
0
Foreground screen UGM
Frame buffer 0 Frame buffer 1
Background screen Source patterns Display list Typical uses of UGM
4 Gbytes CPU memory space
Figure 3.2 Example of UGM Mapping onto CPU Memory Space
3.2
3.2.1
Q2SD Access
UGM Access Priority
The priority order for control of UGM access is as follows: 1. 2. 3. 4. Refreshing Display Video capture CPU
Rev. 2.0, 09/02, page 34 of 366
5. Others (command fetches, drawing, source referencing, etc.) To enable these different kinds of processing to be performed in parallel, after performing access for a fixed period, the Q2SD passes the access control to another source. So if three sources are requesting access, for example, they will perform accesses alternately. 3.2.2 UGM Access by the CPU
The CPU can access the UGM as part of the memory space for the CPU. In a write operation, access is possible with a minimum number of wait cycles if there is empty space in the Q2SD's built-in 32-byte FIFO buffer. In a read operation, a number of wait cycles are inserted. The number of wait cycles varies depending on the relationship between the Q2SD operating clock and the display operating clock, and the screen size. The data stored in the FIFO is transferred to the UGM when the rendering start bit in the system control register (the RS bit in SYSR) is set to 1, when the UGM has not been accessed by the CPU for 32 tcyc0 or more, when the FIFO is full, or when the UGM is accessed by the CPU. If a SuperH with MMU is used as the CPU, the UGM should be mapped onto a normal space as SRAM. Data transfer between the CPU and Q2SD is synchronized with the Q2SD's system operating clock. 3.2.3 UGM Access by DMAC
Data in the memory connected to the CPU bus can be transferred between the memory and the UGM using the DMAC. DMA transfer can be used to transfer display list or image data. Single address mode or dual address mode can be used in DMA transfers, since UGM memory addresses are controlled by the Q2SD's built-in address counter. The address mode is specifiable as single address mode or dual address mode. However, only cycle-steal mode can be used as the bus mode. Note that the burst mode is not supported. See section 2.5.3, DMA Writes. 3.2.4 UGM Access by Q2SD
SDRAM can be connected directly to the Q2SD as the UGM. Use of the SDRAM enables the Q2SD to perform memory access in one-cycle (operating clock). SDRAMs that can be used for the UGM are those that have a power supply voltage of 3.3 V and meet the electrical characteristics and the initialization sequence of the Q2SD. When the bus width of the SDRAM is 16 bits, up to two SDRAMs can be used. The following memory configurations can be used:
Rev. 2.0, 09/02, page 35 of 366
* 64-Mbit capacity (1-Mbit x 16 x 4-bank configuration) * 64-Mbit capacity (512-kbit x 32 x 4-bank configuration) * 16-Mbit capacity (512-kbit x 16 x 2-bank configuration) The type of memory is set in the memory mode register (MEMR). 3.2.5 Register Access from the CPU
The Q2SD has address-mapped registers mapped onto the CPU byte address space (H'000 to H'7FF). These registers are divided into five groups--interface control registers, memory control registers, display control registers (including the color palette registers), rendering control registers, and input data control registers. The color palette registers should be access in longwords. The address specification is made by inputting the address from pins A10 to A1 while the &6 pin is in the 0 state. A reserved addresses must not be read from or written to. Reading or writing to these addresses may result in the loss of address-mapped register values, and unpredictable operation by the Q2SD. To control UGM accesses, initial values must be set in the address-mapped registers by the CPU before it accesses the UGM. The setting procedure is shown in 1 to 3 below. 1. Set initial values in the system control register (SYSR). Set SRES = 0, DRES = 1, and DEN = 0. 2. Set initial values in other registers. 3. Set SRES = 0 and DRES = 0. Also, since video control related registers (video area start address register 0 to 2 (VSAR0 to VSAR2), video window size registers (VSIZER), and video incorporation mode register (VIMR)) are externally updated for video capture operations, they should only be rewritten when the VIE bit is cleared to 0 in the video incorporation mode register. The same also applies when updating bits other than VIE in VIMR. The procedure is shown below. 1. 2. 3. Clear the VIE bit to 0 in VIMR. Retain bits other than VIE to the values to which they are set at that time. Modify the contents of VSAR0 to 2 and VSIZER, and bits other than the VIE bit in VIMR after the elapse of one 996 cycle. Set the VIE bit to 1 in VIMR. Retain bits other than VIE to the values to which they are set at that time.
Rev. 2.0, 09/02, page 36 of 366
3.2.6
Register Updating
External Updating: In external updating, values set in address-mapped registers by the CPU become effective after the end of the CPU access. When the VBK flag and FRM flag in the status register (SR) are set to 1 at the start of vertical blanking, display control related registers which are updated by the external updating, such as the color palette registers, are updated without causing display flicker. Internal Updating: In internal updating, values set in address-mapped registers become effective when Q2SD internal updating is performed. In the case of registers with an internal update function, therefore, display flicker can be prevented even if the CPU modifies addressmapped registers relating to display operations without being aware of the display timing. Internal updating is carried out while the DRES bit is set to 1 in the system control register (SYSR) and at the beginning of each frame. Internal updating is also performed at the beginning of each field for WRAP and BG bits in the display mode register (DSMR), and BGSX and BGSY bits in interlace sync & video mode. The update is performed at the falling edge of 96<1& when the TV sync mode setting in DSMR is TVM1 = 0, TVM0 = 0 (master mode), and on detection of the fall of (;96<1& when TVM1 = 1 and TVM0 = 0 (TV mode). Internal updating is not performed when TVM1 = 0 and TVM0 = 1. The address-mapped registers provided with an internal update function are shown in table 3.1. The initial values of these registers should be set while the DRES bit is set to 1. However, internal updating is used for display start address registers 0, display start address register 1, and the GBM bits in the rendering mode register in display operations. In drawing operations, external updating is used. Internal updating is used for the video area start address (VSAR 0 to 2), video area start coordinates (VPR), and video display size (VSIZE) in display operations. In video capture operations, external updating is used.
Rev. 2.0, 09/02, page 37 of 366
Table 3.1 *
Registers with Internal Update Function
Q2 Control Registers
Name System control register Display mode register Rendering mode register Display mode 2 register Abbreviation SYSR DSMR REMR DSMD2 Bits with Internal Update Function DEN (bit 13) WRAP (bit 11) BG (bit 10) GBM (bits 2-0) All bits
Address A[10:0] H'000 H'00A H'00C H'056
*
Memory Control Registers
Name Display size register X Display size register Y Display start address register 0 Display start address register 1 Background start coordinate register X Background start coordinate register Y Abbreviation DSRX DSRY DSAR0 DSAR1 BGSRX BGSRY Bits with Internal Update Function All bits All bits All bits All bits All bits All bits
Address A[10:0] H'010 H'012 H'014 H'016 H'04C H'04E
*
Display Control Registers
Name Display window register (horizontal display start position) Display window register (horizontal display end position) Display window register (vertical display start position) Display window register (vertical display end position) Horizontal sync pulse width register Horizontal scan cycle register Vertical sync position register Vertical scan cycle register Abbreviation DSWR (HDS) DSWR (HDE) DSWR (VDS) DSWR (VDE) HSWR HCR VSPR VCR Bits with Internal Update Function All bits All bits All bits All bits All bits All bits All bits
Address A[10:0] H'026 H'028 H'02A H'02C H'02E H'030 H'032 H'034
Rev. 2.0, 09/02, page 38 of 366
*
Display Control Registers (cont)
Name Color detection register H Color detection register L Video display position register (horizontal display start position) Video display position register (vertical display end position) Video area start address register 0H Video area start address register 0L Video area start address register 1H Video area start address register 1L Video area start address register 2H Video area start address register 2L Video window size register X Video window size register Y Cursor register (horizontal start position 1) Cursor register (vertical start position 1) Cursor register (horizontal start position 2) Cursor register (vertical start position 2) Cursor area start address register 1 Cursor area start address register 2 Abbreviation CDERH CDERL VPR (HVP) VPR (VVP) VSA0H VSA0L VSA1H VSA1L VSA2H VSA2L VSIZERX VSIZERY CSR (HCS1) CSR (VCS1) CSR (HCS2) CSR (VCS2) CSAR1 CSAR2 Bits with Internal Update Function All bits All bits All bits All bits All bits All bits All bits All bits All bits All bits All bits All bits All bits All bits All bits All bits All bits All bits
Address A[10:0] H'03A H'03C H'058 H'05A H'062 H'064 H'066 H'068 H'06A H'06C H'06E H'070 H'074 H'076 H'078 H'07A H'07C H'07E
3.2.7
Byte Exchange Function
The word data can be replaced between upper and lower data in byte units by using the DTP and MDTP of the input data transfer mode register (IEMR). MDTP is referenced when the data is directly transmitted to the UGM, and DTP is referenced when the data is transmitted to the UGM via the image data entry register (IDER).
Rev. 2.0, 09/02, page 39 of 366
Main memory H'AA H'CC H'EE H'BB H'DD H'FF
Q2SD H'AA H'BB H'BB H'DD H'FF
UGM H'AA H'CC H'EE
....
....
....
1 word
H'BB
H'AA
1 word
Figure 3.3 Byte Exchange Diagram 3.2.8 2-Dimensional Image Data Exchange Function
Conversion of 2-dimensional image data: Image data which is stored in the linear address format in the main memory, etc., can be converted to the two-dimension image data and transferred to UGM. When the image data is transmitted to the image data entry register (IDER) using the CPU, the Q2SD converts the data to the two-dimension image data and stores it in UGM. The supported data format is shown below. For details of the data format, section 3.2.9, Input Color Data Configurations, and section 3.2.10, Configurations of Data in UGM.
IDER Input Data Linear address YUV data (Y, U, V 4 bits each) Linear address (YUV data (4:2:2 format)) Linear address (16 bits/pixel data) Linear address (8 bits/pixel data) UGM Data Two-dimension RGB data (R: 5 bits, G: 6 bits, B 5 bits) Two-dimension RGB data (R: 5 bits, G: 6 bits, B 5 bits) Two-dimension 16 bits/pixel data Two-dimension 8 bits/pixel data
The converted RGB data can be used for the source data of the 4-vertex screen drawing command and the data for each display screen. Q2SD registers that should be set by the CPU are shown in figure 3.4. Make the register settings in the order shown in figure 3.5.
Rev. 2.0, 09/02, page 40 of 366
....
Memory width (512 or 1024 dots) is specified by the MWX bit in the rendering mode register (REMR) Main memory Q2SD internal registers Start address (ISAR) Linear address image data (a) ISAR: Image data transfer start address (b) IDSRX, Y: Image data size (c) IEMR: Input data conversion mode (d) IDER: Image data entry Y size (IDSRY) Two-dimension data X size (IDSRX) UGM source area
Figure 3.4 Image Data Specifications
Set the following: (a) ISAR: image data transfer start address (b) IDSRX, Y: image data size
(c) Set IEMR (bits YUV2, 1, 0): input data conversion mode The setting procedure is shown in the following table. Values to Be Set in YUV2, YUV1, YUV0 Setting Procedure YUV2 YUV1 YUV0 Set (0, 0, 1) in (YUV2, 1, 0). 1 0 0 Set (0, 1, 0) in (YUV2, 1, 0). 0 1 0 Set (0, 0, 0) in (YUV2, 1, 0), then 1 1 0 set (0, 1, 1) in (YUV2, 1, 0). Set (1, 0, 0) in (YUV2, 1, 0), then 1 1 1 set (1, 1, 1) in (YUV2, 1, 0).
(d) Write to IDER: image data entry
Figure 3.5 Register Setting Procedure for YUV/YUV-to-RGB Conversion 2. Sample settings for two-dimension image by DMA transfer When performing two-dimension image conversion by DMA transfer, ensure that the number of pixels corresponding to DMA transfer word count registers H and L (DMAWRH, DMAWRL) is the same as the total number of pixels specified by image data size registers X and Y (IDSRX, IDSRY).
Rev. 2.0, 09/02, page 41 of 366
If these two values are not the same, DMA transfer will end at the smaller of the two values, and then bits YUV2, YUV1, and YUV0 will be cleared to 000, and bits DMA1 and DMA0 will be cleared to 00 again. Therefore, if the total transfer word count of the source data is larger than the DMA transfer word count, DMAWR, the DMA setting must be divided into a number of stages. The image data transfer start address register (ISAR) must be set each time this conversion is performed. 3. An example of the settings for transferring 320 x 240 YUV source data to UGM by means of four DMA_YUV operations
H'000000 320 320 320 240 60 60 60 60 240

YUV source Q2SD RGB data
Figure 3.6 Example of Settings for Transferring 320 x 240 YUV Source Data to UGM by Means of Four DMA Operations Conditions: * * * * YUV source size: Number of setting stages: UGM transfer destination address: YUV mode: 320 x 240 dots 4 H'000000 YUV-RGB conversion
* 1st time (1) Image data transfer start address setting ISAR = H'000000 *1 (2) Image data transfer size register settings IDSRX = 320 IDSRY = 60 *2 (3) DMA transfer word count setting DMAWR = 19200 (4) YUV mode setting IEMR = H'01 (5) DMA mode setting DMA in SYSR = H'11 (6) Wait until the DMF bit in the status register (SR) changes to 1. * 2nd time onward *3 (7) Image data transfer start address re-setting ISAR = current ISAR + transfer word count (Y) = H'C180
Rev. 2.0, 09/02, page 42 of 366
(8) Image data transfer size register settings IDSRX = 320 IDSRY = 60 *5 (9) DMA transfer word count setting DMAWR = 19200 (10) YUV mode setting IEMR = H'01 (11) DMA mode setting DMA in SYSR = H'11
*4
Steps (6) to (11) are then repeated until the end of the YUV transfer source. Settings for YUV-RGB conversion are also made as shown in the above example. Notes: 1. Where IDSRX and IDSRY satisfy the following conditions: * The transfer unit is a line. * One transfer is within the DMAWR range. 2. Set the transfer word count corresponding to IDSRX/IDSRY. 3. In the Q2SD, addresses of the foreground screen area are allocated as shown in section 3.3.2, Memory Map. Therefore, set the drawing data transfer start address in ISAR with reference to the relationship between memory physical addresses and coordinates shown in figure 3.9). In this setting example, the start position of the second image data transfer is at the [X = 0, Y = 60] dot position. This position is divided into the upper and lower coordinates of X and Y, respectively, and the value assigned in figure 3.9 is the value set in ISAR the second time. Example: Method of calculating second ISAR, with memory width of 512 (from figure 3.9)
Y upper Y= Y lower
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 IDSYR = 60
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 IDSYR x 512 value
+
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Current ISAR 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 Calculation result = H'C180
Rev. 2.0, 09/02, page 43 of 366
Example: Method of calculating second ISAR, with memory width of 1024 (from figure 3.9)
Y upper Y= Y lower
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 1 1 1 0 0 IDSYR = 60
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 IDSYR x 1024 value
+
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Current ISAR 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 Calculation result = H'18180
Notes: 4. Same setting conditions as for (2). 5. Same setting conditions as for (3). 3.2.9 Input Color Data Configurations
Input data configurations are shown below. The pixel number starting with 0 runs from left to right in ascending order. * 16-bit data
D15 to D0 Pixel no. 1 word 15 0
*
8-bit data
D15 to D0 Pixel no. 15 1 1 byte 87 0 1 byte 0
*
1 bit/pixel data
D15 to D0 Pixel no. 15 14 15 14 1 word 0 0
Rev. 2.0, 09/02, page 44 of 366
*
8-bit/pixel data
D15 to D0 Pixel no. 15 1 1 word 87 0 0
*
RGB data (16-bit/pixel data)
D15 to D0 15 R (5 bits) 11 10 G (6 bits) 1 word 54 B (5 bits) 0
*
YUV data YUV data uses a 4:2:2 format. The U and V data is horizontally reduced data.
D15 to D0 Image data (1st word) D15 to D0 Image data (2nd word) D15 to D0 Image data (3rd word) D15 to D0 Image data (4th word) 15 Y3 15 Y2 87 V2 15 Y1 87 U2 0 15 Y0 87 V0 0 Data flow 87 U0 0 0
D15 to D0 Image data (nth word)
15 Yn-1
87 Vn-2 1 word
0
n: Even number
Rev. 2.0, 09/02, page 45 of 366
*
YUV data YUV data uses a raster as the basic unit. The data configuration for one raster consists of the initial value in the first two words and compressed image data in the remaining words.
D15 to D0 Initial value (1st word) 15 0 1 word D15 to D0 Initial value (2nd word) 15 U 1 word D15 to D0 Image data (3rd word) 15 U0 12 11 Y0 1 word D15 to D0 Image data (4th word) 15 U2 12 11 Y2 1 word 87 V2 43 Y3 0 87 V0 43 Y1 0 87 V 0 87 Y 0
Data flow
D15 to D0 Image data (nth word)
15 Un-2
12 11 Yn-2
87 Vn-2 1 word
43 Yn-1
0
Rev. 2.0, 09/02, page 46 of 366
*
YCbCr data The data is input from the video capture input. The YCbCr data is eight bits in 4:2:2 format.
VIN7 to VIN0 Image data (1st byte) VIN7 to VIN0 Image data (2nd byte) VIN7 to VIN0 Image data (3rd byte) VIN7 to VIN0 Image data (4th byte) VIN7 to VIN0 Image data (5th byte) VIN7 to VIN0 Image data (6th byte) VIN7 to VIN0 Image data (7th byte) VIN7 to VIN0 Image data (8th byte) 7 Y3 7 Cr2 0 7 Y2 0 7 Cb2 0 7 Y1 0 Data flow 7 Cr0 0 7 Y0 0 7 Cb0 0 0
VIN7 to VIN0 Image data (nth byte)
7 Yn
0
3.2.10
Configurations of Data in UGM
The UGM data configuration is shown below (first for a UGM 16-bit bus, then for a 32-bit bus). The image data is handled as little endian format by the Q2SD. The pixel number starting with 0 runs from left to right in ascending order. * 16-bit data
MD15 to MD0 15 0
1 word MD31 to MD0 31 Address 4n + 2 1 word 16 15 Address 4n 1 word 0
Rev. 2.0, 09/02, page 47 of 366
*
1-bit/pixel data
MD15 to MD0 Pixel no. 15 14 15 14 1 word MD31 to MD0 31 30 31 30 1 word 16 15 14 16 15 14 1 word 0 0 0 0
*
8-bit/pixel data
MD15 to MD0 Pixel no. 15 1 1 word 31 3 1 word 24 23 2 16 15 1 1 word 87 0 0 87 0 0
MD31 to MD0 Pixel no.
*
RGB data (16-bit/pixel data)
MD15 to MD0 15 R (5 bits) 11 10 G (6 bits) 1 word MD31 to MD0 31 27 26 R1 (5 bits) G1 (6 bits) 1 word 21 20 B1 (5 bits) 16 15 11 10 R0 (5 bits) G0 (6 bits) 1 word 54 B0 (5 bits) 0 54 B (5 bits) 0
Rev. 2.0, 09/02, page 48 of 366
*
YCbCr data (YUV data) YCbCr (YUV) data uses a 4:2:2 format. Cr and Cb (U and V) data is horizontally reduced data.
MD15 to MD0 Image data (1st word) MD15 to MD0 Image data (2nd word) MD15 to MD0 Image data (3rd word) MD15 to MD0 Image data (4th word) 15 Y3 15 Y2 87 Cr2 (V2) 15 Y1 87 Cb2 (U2) 0 15 Y0 87 Cr0 (V0) 0 Data flow 87 Cb0 (U0) 0 0
MD15 to MD0 Image data (nth word)
15 Yn-1
87 Cn-2 (Vn-2) 1 word
0
n: Even number
31 MD31 to MD0 Image data (1st longword) 31 MD31 to MD0 Image data (2nd longword) 31 MD31 to MD0 Image data (nth longword) Y2n-1 Y3 Y1
24 23 Cr0 (U0) 24 23 Cr2 (U2)
16 15 Y0 16 15 Y2
87 Cb0 (V0) 87 Cb2 (V2)
0
0 Data flow
24 23 Cr2n-2 (U2n-2) 1 word
16 15 Y2n-2
87 Cb2n-2 (V2n-2) 1 word
0
3.2.11
Q2SD Internal Data Format
Color data configurations in the Q2SD are shown below. * RGB data The display data configurations used in the display unit is shown below. When the UGM data is 16 bits/pixel and the color palette is not used A pixel with H'0000 on the foreground or cursor screen is a transparent color and the data on the lower screens shows through regions set to this color.
DD17 to DD0 17 R (5 bits) MSB 12 11 0 G (6 bits) LSB 18 bits 65 B (5 bits) MSB 0 0 LSB
LSB MSB
Rev. 2.0, 09/02, page 49 of 366
When the UGM data is 8 bits/pixel and the color palette is used, or the UGM data is YCbCr format A pixel with H'00000000 on the foreground or cursor screen is a transparent color and the data on the lower screens shows through regions set to this color.
DD17 to DD0 17 R (6 bits) MSB 12 11 G (6 bits) LSB 18 bits 65 B (6 bits) MSB LSB 0
LSB MSB
DD17 to DD0 are internal signals. Q2SD analog output is the result of D/A conversion of the above data. * Color palette register color data configuration The color palette register color data configuration is shown below. H'0000 0000 is a transparent color and the data on the lower screens shows through regions set to this color.
Register address D15 to D0 Even word MSB D15 to D0 Odd word MSB 15 G (6 bits) LSB MSB 1 word 10 9 8 7 B (6 bits) LSB 2 1 15 8 7 R (6 bits) LSB 0 2 1 0
3.2.12
Interrupt Output Function
The Q2SD outputs interrupt output signal caused by various sources. The generation of interrupt source is reflected in the status register (SR). The selection of interrupt source is set in the interrupt enable register (IER) for use by transfer of the display list or source data to UGM, controlling cursor blinking, controlling DMA transfer, and error processing, etc.
Rev. 2.0, 09/02, page 50 of 366
Table 3.2
Status Register (SR) Bit TVR FRM DMF CER VBK TRA CSF BRK
Interrupt Output Function
Description The expected signal ((;96<1&) is not input The display frame is switched DMA transfer is completed Invalid command is detected The display field is switched The TRAP command is executed The frame is changed before the completion of the command Command execution is aborted by the RBRK bit of the system control register (SYSR)
Processing Error processing Drawing processing, display processing, and data transfer processing Data transfer processing Error processing Drawing processing, display processing, and data transfer processing Drawing processing, display processing, and data transfer processing Error processing Drawing is aborted and restarted. Debugging by software is performed.
3.3
3.3.1
Unified Graphics Memory (UGM)
Memory Address
(1) One Memory Unit The Q2SD performs UGM address control. The UGM includes the display list area, binary source area, 8-bit/pixel or 16-bit/pixel source area, 8-bit/pixel or 16-bit/pixel rendering area, binary work area, and video area. The UGM is configured in 512-byte units, and a different memory configuration is used for each area. The memory configuration for each of the areas is shown in figure 3.7. The UGM consists of addresses that are consecutive within one memory unit (linear addresses), as shown in figure 3.8.
Rev. 2.0, 09/02, page 51 of 366
1-bit/pixel (work, binary source, display list): 1 word H'00 Bit 0 H'00 Bit 1 .... H'00 Bit F H'01 Bit 0 4096 bits 8 bits/pixel (multi-valued source, multi-valued destination):
...... H'00 H'00 H'01 Lower byte Upper byte Lower byte ...... H'0F Upper byte
....
H'FF Bit 0
H'FF Bit 1
....
H'FF Bit F
16 lines
H'F0 H'F0 H'F1 Lower byte Upper byte Lower byte 32 bytes
....
......
H'FF Upper byte
8 bi
16 bits/pixel (multi-valued source, multi-valued destination, video): ...... H'00 H'01 ...... H'0F 16 lines
....
H'F0
H'F1
...... 16 words
H'FF
....
16 b
its
Figure 3.7 Configuration of One Memory Unit (512 Bytes)
Rev. 2.0, 09/02, page 52 of 366
....
ts
512 or 1024 dots 32 bytes 16 lines
16 lines
One memory unit (512 bytes)
Figure 3.8 UGM Address Transitions (2) 2-dimensinal Virtual Addresses The Q2SD handles the UGM as a 2-dimensinal virtual address space. The 2-dimensinal virtual address space is represented by the X-axis corresponding to the horizontal direction of the display and the Y-axis corresponding to the vertical direction. The original corresponds to a physical address of H00 in the UGM. The possible range on the X-axis is from 0 to 511 or from 0 to 1023, and that on the Y-axis is 0 or greater. The Q2SD processes displaying and drawing based on the 2-dimensinal virtual addresses. Conversion between 2-dimensinal virtual addresses and UGM physical addresses shown in figure 3.9 is performed by the Q2SD. The upper bits of the X coordinate and lower bits of the X coordinate refer to the values when the X values are divided into the respective bit widths. Similarly, the Y upper coordinate and Y lower coordinate are the values when the Y values are divided. When the CPU directly accesses the UGM to modify the image data, take this conversion account into consideration. (3) Linear Addresses The Q2SD can handle part of the UGM as a linear address space. The area should be specified to the linear address space and the start address in the UGM should be specified. The addresses of this area is represented by physical addresses.
Rev. 2.0, 09/02, page 53 of 366
8 bits/pixel, MWX = 0 (512 pixels)
A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Upper bits of Y coordinate Upper bits of X coordinate Lower bits of Y coordinate Lower bits of X coordinate
8 bits/pixel, MWX = 1 (1024 pixels)
A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Upper bits of Y coordinate Upper bits of X coordinate Lower bits of Y coordinate Lower bits of X coordinate
16 bits/pixel, MWX = 0 (512 pixels)
A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Upper bits of Y coordinate Upper bits of X coordinate Lower bits of Y coordinate Lower bits of X coordinate 0
16 bits/pixel, MWX = 1 (1024 pixels)
A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Upper bits of Y coordinate Upper bits of X coordinate Lower bits of Y coordinate Lower bits of X coordinate 0
Upper line: UGM physical addresses (bytes) A22 to A1, A0 Lower line: 2-dimensional virtual addresses (X, Y)
Note: A0 is an LSI internal signal, indicating the least significant bit of the byte address. The least significant bit of the byte address is decoded and output to pins UDQM0, UDQM1, LDQM0 and LDQM1.
Figure 3.9 Correspondence between UGM Physical Addresses (Bytes) and 2-Dimensinal Virtual Addresses (4) Work Addresses The Q2SD handles part of the UGM as a work address space. Work addresses are 2-dimensinal addresses and one dot corresponds to one address. The work address space starts from the address specified by the work area start address register (WSAR). The work address space configures a 2-dimensional space by wrapping around at every 512 or 1024 pixels. The number of pixels for wrap-around is specified by the memory width bit in the rendering mode register (the MWX bit in REMR). Figures 3.10 and 3.11 show the examples.
Rev. 2.0, 09/02, page 54 of 366
The memory capacity required for the work address space is (the number of pixels specified by the MWX bit) x (YMAX in the SCLIP command + 1)/8 [bytes]. In general, one less than the number of display lines in the vertical direction should be set as YMAX in the SCLIP command.
0
511
512 Work area 544 Display list and binary source
Work area start address: H'40000 Display list start address: H'44000 Conditions: 8 bits/pixel 512-pixel memory width (MWX = 0)
Figure 3.10 Work Address Space
LSB
MSB
Work address X 0 8 dots 0 1 H'40000 H'40040 . . H'401C0 8 dots H'40001 H'40041 . . H'401C1 ...... ...... ...... . . ...... 8 dots H'4003F H'4007F . . H'401FF 1 memory unit (512 bytes) = 1 line of work address space 32 memory units = 32 lines of work address space 511 UGM physical address
Work address Y
. . 7
. .
. .
. .
. .
. .
255
H'43FC0
H'43FC1
......
H'43FFF
Work area start address H'40000
Figure 3.11 Relationship between UGM Physical Addresses (Byte) and Work Addresses
Rev. 2.0, 09/02, page 55 of 366
(5) UGM Physical Addresses The UGM addresses range from H000000 to H37FFFE when two memories of 16 Mbits x 16 or from H000000 to H7FFFFE when a single memory of 64 Mbits x 32. 3.3.2 Memory Map
Figure 3.12 shows a memory map of the UGM. A combination of 8-bit/pixel and 16-bit/pixel areas can be used in the UGM, but area allocation must be carried out so that areas do not overlap. For this purpose, 8-bit/pixel and 16-bit/pixel areas should virtually be considered as shown in figure 3.13 when performing area allocation. In terms of the number of Y-direction dots, there is a 2-to-1 relationship between the 8-bit/pixel and 16-bit/pixel memory maps.
Rev. 2.0, 09/02, page 56 of 366
[DSA0] (X = 0, Y = 256l) 0 (0, 0)
X
(639, 0)
(1023, 0)
UGM
Y Foreground screen (FG) (frame buffer FB0)
479 512 [DSA1] (X = 0, Y = 256l) Foreground screen (FG) (frame buffer FB1)
BGSY [VSAH0, VSAL0] Video area (V0) [DLSAH, DLSAL] Display list 1 [WSAH, WSAL] (X = 0, Y = 16n) Display list 2 [WSAH, WSAL] Work area [SSAH, SSAL] (X = 0, Y = 16m) [SSAH, SSAL] Multi-valued source area [VSAH1, VSAL1] Video area (V1) [VSAH2, VSAL2] Video area (V2)
(BGSX, BGSY) BGSX Background screen (BG)
[CSAH1, CSAL1] A A [CSAH2, CSAL2] B B Cursor 1 with blink function Cursor 2 with blink function
l, m, n: Multiplier
Figure 3.12 Sample Memory Map (Corresponding to 640 x 480 Screen Size, with 16 Bits/Pixel )
Rev. 2.0, 09/02, page 57 of 366
16 Mbits x 2
* * * * *
[WSAH, WSAL]: Addresses which can be specified by bits A22 to A13 [SSAH, SSAL]: Addresses which can be specified by bits A22 to A13 [DSA0], [DSA1]: Addresses which can be specified by bits A22 to A16 [DLSAH, DLSAL]: Addresses which can be specified by bits A22 to A5 [VSAHn, VSALn]: Addresses which can be specified by bits A22 to A10 (n = 0, 1, and 2)
0
0 FB0
1023 UGM
0
UGM
1023 0
512 FB1 1024 (dots) 16-bits/pixel memory map
512 (dots)
8-bits/pixel memory map
Figure 3.13 Relationship between 8-Bits/Pixel and 16-Bits/Pixel Memory Maps
Rev. 2.0, 09/02, page 58 of 366
If a 1024-pixel memory width configuration is used when the horizontal screen size is 512 pixels or less (e.g. 320 x 240 equivalent), the foreground screen FB1 can be set from position X = 512 by setting the HDIS bit in display mode register 2 (DSMR2) to 1. In this case, the same value is set in DSA0 and DSA1. When the HDIS bit is set to 1, use the following settings: GBM2 = 0, BM1 = 0, and RSAE = 0.
3.3.3
(1) Coordinates
The Q2SD has screen coordinates for display control, rendering, work, multi-valued source, and binary source coordinates for drawing control, and foreground screen, background screen, video screen, and cursor coordinates for display screen. In the Q2Sd 2-dimensional coordinates, a set of coordinates indicates a single pixel (except for video coordinates in YCbCr format). An X coordinate corresponds to the horizontal direction of the display screen and a Y coordinate corresponds to the vertical direction. The positive coordinates indicate the right direction for X coordinates and the lower direction for Y coordinates.
,
, " !
0 1023 0 512 1023 FB0 FB0 FB1 FB1 MWX = 1 HDIS = 0 MWX = 1 HDIS = 1
Figure 3.14 Example of Frame Buffer FB1 Location When HDIS = 1
Coordinate Systems
There are three types of the correspondences between coordinates and UGM addresses: 2dimensional virtual addresses, linear addresses, and work addresses. The coordinates in which addresses can be handled as 2-dimensional virtual addresses are screen, rendering, multi-valued source, foreground screen, background screen, and video screen coordinates. However, the multi-valued source coordinates are handled as 2-dimensional virtual addresses only when LNi =
Rev. 2.0, 09/02, page 59 of 366
0 (source linear specification of the rendering attribute). The coordinates in which addresses can be handled as linear addresses are multi-valued source, binary source, and cursor coordinates. The coordinates in which addresses can be handled as work addresses are work coordinates. For details of the 2-dimensional virtual, linear, and work addresses, see section 3.3.1, Memory Address. (2) Screen Coordinates The screen coordinates are for display control. The origin of this coordinates corresponds to the upper-left of the display area. A step of the X coordinates corresponds to a dot and a step of the Y coordinates corresponds to a line (one raster). For example, the upper-left and lower-right coordinates of the yw-by-xw display area are (0, 0) and (xw - 1, yw - 1) in the screen coordinates. The correspondences vary in each display screen. The origin of the foreground screen corresponds to that of the screen coordinates. The start coordinates of the background screen are the same as that of the screen coordinates. The origins of the video and cursor screens are within the screen coordinates specified by the video display start position registers (VPR) and cursor display start position registers (CSR). The maximum X values in the screen coordinate is 1023 or 511 which is specified by the memory width bit in the rendering mode register (the MWX bit in REMR).
(0, 0)
Foreground screen origin Background screen start coordinates Video screen origin (HVP - 1, VVP - 1) Max. setting Cursor 1 screen origin (HCS1 - 1, VCS1 - 1) 1023 Min. setting 511 Cursor 2 screen origin (HCS2 - 1, VCS2 - 1)
X
(XW - 1, YW - 1)
Y
Screen coordinates
Figure 3.15 Screen Coordinates
Rev. 2.0, 09/02, page 60 of 366
(3) Rendering Coordinate System This is the coordinate system used for drawing control as destination coordinates for drawing commands. It has a fixed size as shown in figure 3.15. The coordinates which exceeds the fixed size cannot be handled. The origin of the rendering coordinates corresponds to the display address register (DSAR0 and DSAR1) contents when the RSAE bit in the rendering mode register (REMR) is cleared to 0, and the rendering start address register (RSAR) contents when the RSAE bit in the rendering mode register (REMR) is set to 1. Eight bits or 16 bits of data width (8 bits/pixel or 16 bits/pixel) for a set of the rendering coordinates can be selected by the graphic bit mode bits in the rendering mode register (bits GBM 2 to GBM 0 in REMR). Drawing operations for coordinates outside the clipping area are performed. However, accesses to the UGM are not performed. The rendering coordinates origin can be shifted in both horizontal and vertical directions by the offset specified by the local offset command (LCOFS). In this case, the coordinates to which the offset values XO and YO specified by the LCOFS command are added must be within the range shown in the following expressions. Of all drawing commands, the commands which specifies clipping (SCLIP and UCLIP) are handled as the rendering coordinates without offset. (When bold line attribute is specified)
-2045 X + XO 2044 -2045 Y + YO 2044
(When bold line attribute is not specified)
-2048 X + XO 2047 -2048 Y + YO 2047
Rev. 2.0, 09/02, page 61 of 366
-2048
When offset values = 0
-2048
Rendering coordinate origin (0, 0) X 2047
2047 Y Rendering coordinates
When offset values = (a, b) -2048 The size of the logical space from the rendering coordinate origin in accordance with the offset values never exceeds 2047.
Rendering coordinate origin (without offset) (0, 0) -2048 Offset 2047-a X (a, b) Rendering coordinate origin (with offset)
2047-b Rendering coordinates Y -2048+b
-2048+a
Rendering coordinate origin (with offset) (-a, -b) X 2047 Offset (0, 0) Rendering coordinate origin (without offset)
When offset values = (-a, -b) The size of the logical space from the rendering coordinate origin in accordance with the offset values never exceeds 2047.
2047
Rendering coordinates Y
Figure 3.16 Rendering Coordinates
Rev. 2.0, 09/02, page 62 of 366
(4) Multi-Valued Source Coordinates This is the coordinate system used for drawing control and handles multi-valued source data (graphics bit map data and natural images) specified by drawing commands. Data width of 8 bits or 16 bits for a set of the multi-valued source data coordinates (8 bits/pixel or 16 bits/pixel) can be selected by the graphic bit mode bits in the rendering mode register (bits GBM 2 to GBM 0 in REMR). Data width of the multi-valued source coordinates is determined by the bit configuration specified by this register setting. The Q2SD can use two kinds of multi-valued source coordinates according to the value of linear attribute LNi. When LNi = 0, the coordinate origin is specified by the multi-valued source area start address. Figure 3.17 shows the multi-valued source coordinates when LNi = 0. As shown in this figure, the maximum coordinate system size is represented by 1024 x 1024 positive coordinates, but the size depends on the installed memory capacity, screen size, and multi-valued source area start address. Depending on the multi-valued source start address, this coordinate system may entirely or partially overlap another coordinate system. When data is transferred from the CPU, address conversion shown in figure 3.9 is needed. If the function of 2-dimensional image data conversion is used (see section 3.2.8, 2-Dimensional Image Data Exchange Function), the address conversion shown in figure 3.9 is performed by the Q2SD. When LNi = 1, it is possible to use multi-valued source arranged in linear fashion in the UGM. The physical address of the origin and the range of the coordinates are specified by the parameters in a drawing command. Each multi-valued source data indicates one physical address (origin: upper-left of the multi-valued source data coordinates) and specify the area (length and width) by the source address parameters (TDX and TDY) in the POLYGON4A command. This area can overlap another coordinate system such as a display list. Figure 3.18 shows the multivalued source coordinates when LNi = 1.
Rev. 2.0, 09/02, page 63 of 366
SSAR
(0, 0)
(MAX) 1023
X
(MAX) 1023
Y
Figure 3.17 Multi-Valued Source Coordinates (LNi = 0)
TDX Source address (byte) (0, 0) TDY POLYGON4A command parameters * Source address * TDX * TDY
Figure 3.18 Multi-Valued Source Coordinates with LNi = 1 Specified (Linear Address) (5) Binary Source Coordinates This is the coordinate system used for drawing control and handles binary source data (character and line patterns) specified by drawing commands. Data width of a single bit for a set of the binary source data coordinates (1 bit/pixel) is used. The physical address of the origin and the range are specified by the parameters in a drawing command. Each binary source data indicates one physical address (origin: upper-left of the binary source data coordinates) and specify the area (length and width) by the source address parameters (TDX and TDY) in the POLYGON4B command. This area can overlap another coordinate system such as a display list. However, the start address of the source pattern must be a byte address.
Rev. 2.0, 09/02, page 64 of 366
TDX Source address (byte) (0, 0) TDY POLYGON4B command parameters * Source address * TDX * TDY
Figure 3.19 Binary Source Coordinates (6) Work Coordinate System This coordinate system is for drawing control and corresponds on a one-to-one basis to the rendering coordinate system, as shown in figure 3.20. When the work specification in the rendering attributes is set, a pattern is controlled using this coordinates. Drawing commands for work data use this coordinates for drawing. Data width of a single bit for a set of the work coordinates is used. The physical address of the origin, clipping, and offset are controlled the same way as the rendering coordinates. The physical address of the origin is specified by the work area start address register (WSAR)
Rev. 2.0, 09/02, page 65 of 366
When offset values = 0 -2048
Work coordinate origin (0, 0) 2047 -2048 : Physical coordinate space (memory-installed space) 2047 Work coordinates Y : Display space for 320 x 240 screen configuration (system clipping space)
When offset values = (a, b) -2048 The size of the logical space from the work coordinate origin in accordance with the offset values never exceeds 2047.
Work coordinate origin (without offset) (0, 0) -2048 2047-a X Offset (a, b) Work coordinate origin (with offset)
2047-b Work coordinates Y -2048+b
When offset values = (-a, -b) The size of the logical space from the work coordinate origin in accordance with the offset values never exceeds 2047.
-2048+a
Work coordinate origin (with offset) (-a, -b) X 2047 Offset (0, 0) Work coordinate origin (without offset)
2047 Y
Work coordinates
Figure 3.20 Work Coordinates
Rev. 2.0, 09/02, page 66 of 366
(7) Foreground Screen Coordinate System This coordinate system is for display control and the foreground screen (FG(FB0 and FB1)) is handled by this coordinate system. The physical address of the origin is specified by the display start address register (DSAR0 and DSAR1). The display buffer uses the double buffer configuration by which the origin of this coordinates specified by DSAR0 or by DSAR1 as a display start address can be switched. Data width of 8 bits or 16 bits for a set of this coordinates (8 bits/pixel or 16 bits/pixel) can be selected and a maximum value of the X coordinate of 511 or 1023 can also be selected. These settings are specified by the graphic bit mode and memory width bits in the rendering mode register (bits GBM 2 to GBM 0 and the MWX bit in REMR). (8) Background Screen Coordinate System This coordinate system is for display control and the background screen (BG) is handled by this coordinate system. The physical address of the origin is fixed at H0. Display starts from the coordinate specified by the background start coordinate registers (BGSR). Data width of 8 bits or 16 bits for a set of this coordinates (8 bits/pixel or 16 bits/pixel) can be selected and a maximum value of the X coordinate of 511 or 1023 can also be selected. These settings are specified by the graphic bit mode and memory width bits in the rendering mode register (bits GBM 2 to GBM 0 and the MWX bit in REMR). (9) Video Screen Coordinate System This coordinate system is for display control and the video screen is handled by this coordinate system. The physical address of the origin is specified by the video area start address registers (VSR0 to VSR2). The buffer for video capture and display uses the triple buffer configuration by which the origin of this coordinates specified by VSR0, VSR1, or VSR2 as a display (video capture) start address can be switched. Data width of YCbCr and RGB format are 8 bits or 16 bits for a set of this coordinates (8 bits/pixel or 16 bits/pixel), respectively. This is specified by the RGB bit in the video incorporation mode register (VIMR). The area of this coordinates is specified by the video window size registers (VSIZER). (10) Cursor Coordinate System This coordinate system is for display control and the cursor is handled by this coordinate system. The physical address of the origin is specified by the cursor area start address registers (CSAR1 and CSAR2). Display for cursor 1 starts from the origin specified by CSAR1 and display for cursor 2 starts from the origin specified by CSAR2. Data width for a set of this coordinates is 8 bits (8 bits/pixel). Both the X and Y coordinates range from 0 to 31.
Rev. 2.0, 09/02, page 67 of 366
3.3.4
Double-Buffering Control
The Q2SD uses double-buffering control to alternately switch the display and drawing areas located in the UGM. An area switching operation is called a display change. There are three types of mode for double-buffering control: auto display change mode, auto rendering mode, and manual display change mode. These are specified by the double-buffering mode bits (DBM) in the system control register. The start of drawing is specified by the RS bit. When double-buffering control is performed, frame changes are performed in frame units when the Q2SD is operating in non-interlace or interlace mode, and in field units when operating in interlace sync & video mode. When the Q2SD is operated in interlace mode, the frame flag (FRM) in the status register is used for 96<1& synchronization pulse detection by the CPU. When the Q2SD is operated in noninterlace mode, synchronization pulses are detected using the vertical blanking flag (VBK). When the Q2SD is operating in interlace sync & video mode, since the first field corresponds to the even field and the second field to the odd field, synchronization pulses are detected using VBK or FRM. The same results can also be achieved by using the VBKEM command. * Double-buffer switching timing: Non-interlace mode Scanning system in which one frame is composed of one field. Double-buffer switching is performed in units of a frame. Interlace mode Scanning system in which one frame is composed of two fields. Double-buffer switching is performed in units of a frame. Interlace sync & video mode Scanning system in which one frame is composed of two fields. Double-buffer switching is performed in units of a field. Examples are given below for Q2SD non-interlace operation, with a description of the operation in each mode. (1) Auto Display Change Mode In auto display change mode, display changes have priority. Display is changed on completion of the frame. When drawing is completed within a frame periods, this mode can be used. If drawing is in progress when the frame is changed, drawing is aborted midway through that display list. It is therefore essential for drawing to be finished before the arrival of a 96<1& synchronization pulse.
Rev. 2.0, 09/02, page 68 of 366
An outline of operation in this mode is shown in figure 3.21. Drawing cannot be started with the VBKEM command in this mode, so the VBK or FRM flag must be used. Drawing is started by the rendering start bit (RS).
Frame change 1st frame
Frame change 2nd frame
VSYNC (non-interlace operation)
Display screen: FB0 Q2SD operation Drawing destination: FB1
Display screen: FB1 Drawing destination: FB0
Interrupt by VBK flag
Drawing to F1 aborted
*Drawing start
CPU operation
Interrupt handling
Interrupt handling
FB0 display list transfer
*Drawing start
FB1 display list transfer
FB0: Frame buffer 0 FB1: Frame buffer 1 VBK flag: Vertical blanking flag (bit 11 of status register (SR)) Note: Drawing is started by setting the RS bit to 1.
Figure 3.21 Operation in Auto Display Change Mode (2) Auto Rendering Mode In auto rendering mode, display switching is not performed until execution of a TRAP command is completed. If drawing does not end within one frame, it is continued without interruption and display is changed in the frame on completion of drawing. An outline of operation in this mode is shown in figure 3.22. Drawing is started by the rendering start bit (RS).
Interrupt by VBK flag
Rev. 2.0, 09/02, page 69 of 366
1st frame
2nd frame
3rd frame
Rev. 2.0, 09/02, page 70 of 366
Display screen: FB0 Drawing destination: FB1
VSYNC (non-interlace operation)
Display screen: FB1 Drawing destination: FB0
Q2SD operation
Display switching is performed automatically at frame boundary immediately after end of drawing.
CPU operation FB0 display list transfer
Interrupt is generated by VBK flag but is ignored as command has not finished.
Interrupt by VBK flag
Interrupt handling
Interrupt by TRA flag
Interrupt by VBK flag
*Drawing start
*Drawing start
Interrupt handling
Interrupt handling
Figure 3.22 Operation in Auto Rendering Mode
FB0: Frame buffer 0 FB1: Frame buffer 1 VBK flag: Vertical blanking flag (bit 11 of status register (SR)) Note: Drawing is started by setting the RS bit to 1.
FB1 display list transfer
(3) Manual Display Change Mode In manual display change mode, display changes and the start of drawing are controlled independently by software. Frame changes can be performed by software by switching between FB0 and FB1 according to the setting of the DC bit in SYSR, or by using the WPR command to set the FB0 or FB1 start address in the display start address register indicated by DBF in the status register. The start of drawing is controlled by the RS bit in the system control register. Interrupts by means of the VBKEM command or the TRA flag are used for the control timing. An outline of operation in this mode when using the DC bit is shown in figure 3.23. When changing from this mode to another double-buffering control mode, first check that the DC bit has been set to 1 and has then returned to 0. If this is not done, a display change will occur at a timing of VSYNC during display processing. Confirm that the DC bit is cleared to 0 before setting it to 1. (4) Control by Means of VBKEM and WPR Commands The VBKEM command holds fetching and execution of the display list waiting following this command. With the VBKEM command , the waiting state is cleared at the next VSYNC in noninterlace mode display or interlace sync & video mode display, and at the start of the next frame in interlace sync mode display. Use of this command allows drawing processing to be started without using a VBK or FRM interrupt. Control is carried out by a combination of the WPR command, which performs drawing-related register setting, and the VBKEM command, which ends in synchronization with VBK, as shown in figure 3.24. The CPU only has to monitor drawing end interrupts; monitoring of VBK interrupts is no longer necessary. This kind of double-buffering control can be used only in auto-rendering mode and manual display change mode.
Rev. 2.0, 09/02, page 71 of 366
1st frame
2nd frame
3rd frame
Rev. 2.0, 09/02, page 72 of 366
Display screen: FB0 Drawing destination: FB1 Drawing destination: FB0
VSYNC (non-interlace operation)
Display screen: FB1
Q2SD operation
Display area change (DC) bit is set, and screen is switched at next frame boundary.
Interrupt is generated by VBK flag but is ignored as command has not finished.
CPU operation FB0 display list transfer
Interrupt by VBK flag Interrupt by TRA flag
Interrupt by VBK flag
Interrupt handling
*Drawing start
*Drawing start
Interrupt handling
Interrupt handling
Figure 3.23 Operation in Manual Display Change Mode
FB1 display list transfer
FB0: Frame buffer 0 FB1: Frame buffer 1 VBK flag: Vertical blanking flag (bit 11 of status register (SR)) TRA flag: Trap flag (bit 10 of status register (SR)) Note: Drawing is started by setting the RS bit to 1.
0th frame
1st frame
2nd frame
VSYNC (non-interlace operation)
Display screen: FB1 WPR VBKEM Drawing destination: FB1 WPR
Display screen: FB0 VBKEM
Display screen: FB1 Drawing destination: FB0
Q2SD operation
Interrupt by TRA
F1 display list activated. In manual change mode, display area change (DC) bit is set first. Drawing start
Drawing start
Display address etc. set by WPR, synchronization performed by VBKEM.
CPU operation FB0 display list transfer
Interrupt handling
Interrupt handling
Figure 3.24 Operation when Using VBKEM Command
FB0: Frame buffer 0 FB1: Frame buffer 1 VBK flag: Vertical blanking flag (bit 11 of status register (SR)) TRA flag: Trap flag (bit 10 of status register (SR)) Note: Drawing is started by setting the RS bit to 1.
Rev. 2.0, 09/02, page 73 of 366
FB1 display list transfer
3.3.5
Refresh Control
The number of refresh cycles for the UGM connected to the Q2SD is set in bits REF3 to REF0 (refresh cycle count) in the display mode register (DSMR). The setting made in bits REF3 to REF0 is the number of refreshes per line (raster). For example, if the refreshing specification of the memory used is 4096 cycles/64 ms and one field is 1/60 sec, the necessary number of refresh cycles in one field is 1067 cycles. Since the value set in DSMR is the number of refresh cycles per lines (rasters), it is the quotient when 1067 is divided by the number of lines (rasters) in one field. The number of refresh cycles should therefore be set so that the following expression is satisfied: 1067 number of lines (rasters) x number of refresh cycles set in DSMR The Q2SD supports CAS-before-RAS refresh mode. The number of refreshes set in bits REF3 to REF0 are executed from the fall of the DISP signal. Table 3.4 shows sample settings. Table 3.3
Bit 3: REF3 0 *
Setting for Number of Refreshes
Bit 2: REF2 0 * Bit 1: REF1 0 * Bit 0: REF0 0 * Operation Refresh timing is not output. Refresh timing is set to any value from 1 to 15 cycles, and output.
Table 3.4
Display Screen Size 320 x 240 480 x 240 640 x 480
Sample Estimations of Number of Refresh Cycles
Frame Rate 1/60 s 1/60 s 1/60 s Number of Lines 525/2 lines 525/2 lines 525 lines Number of Refreshes Required Per Line (1/60) (2/525) (4096/0.064) = 4.06 (1/60) (2/525) (4096/0.064) = 4.06 (1/60) (1/525) (4096/0.064) = 2.03 REF Set Value 5 5 3
Rev. 2.0, 09/02, page 74 of 366
3.4
3.4.1
Display
Display Functions
The Q2SD has functions for outputting image data, drawn in the UGM, in synchronization with externally or internally generated display timing. In the Q2SD, horizontal and vertical display timing for the display screen is set in the display control registers (see section 5.4, Display Control Registers). The display control register settings depend on the scanning and synchronization systems used. Table 3.5 shows the display control register settings. Figure 3.25 shows the display timing in non-interlace mode. The display screen is defined by the variables shown in table 3.6. Set each of VDC, VDE, VSP, and VC to the number of rasters within one 96<1& cycle for, regardless of the scan mode in the display mode register. Set DSY to the number of rasters within one 96<1& cycle (one field) in non-interlace or interlace mode, or set DSY to two 96<1& cycles (one frame) in interlace sync & video mode. For the display operating clock (display dot clock) frequency, use the value obtained by dividing the number of pixels to be displayed in the xw period by the duration of the xw period. Input the dot clock to the CLK1 pin.
hc hsw xs xw
yw
ys
Display area
Figure 3.25 Display Timing
Rev. 2.0, 09/02, page 75 of 366
vsw
vc
Table 3.5
Variable hc hsw xs xw vc vsw ys yw
Variables Defined by Display Screen
Description Horizontal scan cycle Horizontal sync pulse width Interval between +6<1& rise and display screen horizontal display start position Display screen display width per raster Vertical scan cycle Vertical sync pulse width Interval between 96<1& rise and display screen vertical display start position Display screen vertical display interval Unit Dot clock Dot clock Dot clock Dot clock Raster lines Raster lines Raster lines Raster lines
Rev. 2.0, 09/02, page 76 of 366
Table 3.6
Register Address (A10-A0) 010 012 026 028 02A 02C 02E 030 032 034
Register Settings
Operating Mode Register Name Display size register X (DSRX) Display size register Y (DSRY) Display window Horizontal display start position register (DSWR) Horizontal display end position register (DSWR) Bit Name DSX* DSY HDS* * HDE*
2 23 5
Master Mode xw yw (2yw)*
6
TV Sync Mode xw yw (2yw)*
6
hsw + xs - 11 hsw + xs - 11 + xw ys - 2 ys - 2 + yw hsw - 1 hc - 1
hsw + xs - 14 hsw + xs - 14 + xw ys - 2 ys - 2 + yw hsw - 1 hc vc - vsw - 1 vc + 2
Vertical display start position VDS* * register (DSWR) Vertical display end position VDE* register (DSWR) Horizontal sync pulse width register (HSWR) Horizontal scan cycle register (HCR) Vertical sync position register (VSPR) Vertical scan cycle register (VCR) HSW HC VSP* VC*
1 1 1
14
vc - vsw - 1 vc - 1
Notes: 1. In all scanning mode the settings of the VDS, VDE, VSP, and VC bits are made for a one-field unit. 2. Timing for the HDS and HDE are stipulated from the fourth rising edge of CLK1 after the low level of (;+6<1& is detected at the rising edge of CLK1.
CLK1
3. The setting for the lower limit of the HDS bits is as follows: when MCLK = 2 x CLK1, HDS 64 x (CLK1/MCLK); when MCLK > 2 x CLK1, HDS (64 + 80) x (CLK1/MCLK). The unit for MCLK and CLK1 is MHz. When MCLK = 2 x CLK1, use a clock with which MCLK and CLK1 are synchronized. With a multiplication factor of N, MCLK is N x CLK0. 4. In interlace and interlace sync & video mode, the setting is: VDS 1. 5. Use a value of 4 or more for DSX. If the cursor 1 horizontal display start position (HCS1) and cursor 2 horizontal display start position (HCS2) in the cursor registers are DSX, DSX - 1, DSX - 2, DSX - 3, DSX - 4, DSX - 5, then set DSX = XW + 6. 6. In interlace sync & video mode
Rev. 2.0, 09/02, page 77 of 366
3.4.2
Screen Display Composition
In the Q2SD, the DEN (display enable) bit in the system control register (SYSR) can be used to select whether or not display data is to be output to the screen. When display data is not output, the display off output register (DOOR) settings are displayed. The Q2SD is capable of composing a screen from two cursor screens, a foreground screen (FG), a video screen, and a background screen (BG), and of displaying the screen thus composed. See figure 3.26. The data on the lower screens shows through regions of black (H0) in the cursor and FG screens, since black is the transparent color for these screens. Therefore, characters and pictures drawn on these screens using color other than black are composed with the image on the video screen.
(1) Composed Screen Types
* Foreground screen: FG (frame buffer FB0 or FB1) * Video screen: VW * Background screen: BG * Cursors (cursor1 and cursor2) The foreground screens, video screens, and background screens that can actually be composed depend on the UGM bus width, the Q2SD operating frequency, and the display operating clock frequency. See appendix E. (2) Priority Order of Composed Screens Screens are displayed in the priority order shown below. With the cursors, display can be performed according to the priority order set in the window priority bits (PRI) in display mode register 2 (DSMR2). Foreground screen > video screen > background screen (in front-to-rear order)
,,,
Figure 3.26 Configuration of the Display Screen for Q2SD
,,,,,, ,,,,,,,, ,,,,,, ,,,,,,,, ,,,,,,,, ,,,,,,
Cursor screen Foreground screen (FG) Video screen Background screen (BG)
Rev. 2.0, 09/02, page 78 of 366
(3) Features of Each Screen * Foreground screen (FG) If the data for a foreground screen pixel is H0 (color-expanded data by the color palette when 8 bits/pixel is selected), a low-priority screen such as the video window is displayed through that pixel. * Video screen (VW) In the video screen, the data in the UGM which is specified by the contents of the video area start address registers (VSAH and VSAL) is displayed on a rectangular area specified by the contents of the video window size registers (VSIZE). The video screen is not transparent to a low-display-priority screen such as the background screen and is displayed as a rectangular area. This window displays the video area specified by the video area start address registers (VSAH and VSAL) pointed to by the video window status bit (VID) regardless of whether the video incorporation enable bit in the video incorporation mode register (the VIE bit in VIMR) is set to 1 or cleared to 0. * Background screen (BG) The display start position can be set in background coordinate display start registers X and Y (BGSX, BGSY) in pixel units from address H0 in the UGM. The background screen is suitable for performing scroll display. Setting the wrap around bit in the display mode register (the WRAP bit in DSMR) to 1 enables to access the display area in wrapping around way. When displaying the background screen, ensure that the frame screen and background screen locations in the UGM do not overlap. * Cursors Two 32 x 32-pixel cursors with a hardware blink function can be displayed. If the cursor pixel data color-expanded by the color palette is H0, a low-priority screen is displayed through that pixel. The blink cycle is specified by the cursor blink shape A display interval length or cursor blink shape B display interval length in the cursor display start position registers (the BLINKA or BLINKB bit in CSR). (4) Display on/off control The bits that control whether or not each screen is displayed are shown below. With the foreground and background screens, set either or both to be displayed. When the foreground screen is set to 16-bit/pixel mode with bits GBM2 to GBM0, the Q2SD's internal display data increases and other screens cannot be displayed. Therefore, to disable display of the video window, background screen, and cursors, the bits controlling whether or not each screen is to be displayed should be cleared to 0. In this case, also, clear the VIE bit to 0 in the video incorporation mode register (VIMR) to disable video capture. Register updating for each screen should be carried out in the register update interval shown in section 3.2.6, Register Updating. The display contents differ according to the setting of the background screen wraparound mode (WRAP) bit.
Rev. 2.0, 09/02, page 79 of 366
* * * *
Foreground screen: Can be set with the FBD bit in display mode register 2 (DSMR2). Video screen: Can be set with the VWE bit in display mode register 2 (DSMR2). Background screen: Can be set with the BG bit in the display mode register (DSMR). Cursors: Can be set with bits CE1 and CE2 in display mode register 2 (DSMR2). Table 3.7 Background Screen Related Register Settings
Register Name DSMR REMR BGSRX BGSRY Bit No. 10 11 2 to 0 9 to 0 13 to 0 Field Name BG WRAP GBM BGSX BGSY Set Value 1/0 1/0 000 to 111 BG starting point X coordinate BG starting point Y coordinate Notes Combination on/off Wraparound on/off 8 or 16 bits/pixel According to screen coordinates
512 or 1024 FB0
+
Display screen
BGSY
BGSX BG
Specifies background screen start coordinates BGSX BGSY Scrolling achieved by changing start address
16 Mbits x 1, 8 bits/pixel
Figure 3.27 Example of Background Screen Simple Scroll (WRAP = 0)
Rev. 2.0, 09/02, page 80 of 366
512 or 1024 FB0
+
Display screen
BGSY [13:09]
1 3
2 4
512 pixels (fixed)
4 BGSY BGSX
3
2
1 3'
2' 4'
Performs background screen wraparound. The wraparound unit is a rectangle comprising the memory width specified by the MWX bit in the X direction, and 512 pixels in the Y direction. The start address is given by 0 in the X direction and bits [13:09] of BGSY in the Y direction.
16 Mbits x 1, 8 bits/pixel
Figure 3.28 Example of Background Screen Wraparound Scroll (WRAP = 1) 3.4.3 Scanning Systems
(1) Q2SD Scanning Systems The Q2SD allows selection of non-interlace mode, interlace mode, or interlace sync & video mode as the scanning system. The mode setting is made in the SCM (scan mode) bits in the display mode register (DSMR). In non-interlace mode, one frame is composed of one field. In interlace mode, one frame is composed of two fields, even and odd, in which the same data is displayed. In interlace sync & video mode, also, one frame is composed of two fields, even and odd, but in this mode different data is displayed in these two fields. When the ODEV bit is cleared to 0 in display mode register 2 (DSMR2), the 2'') pin signal functions as follows. The order of fields to be displayed in interlace and interlace sync & video mode is specified by the ODEV bit in the display mode 2 register (DSMR2). When the ODEV bit is cleared to 0, an odd field and an even field for the same frame are displayed in that order. When the ODEV bit is set to 1, an even field and an odd field for the same frame are displayed in that order. In master mode, the Q2SD outputs a high-level signal from the 2'') pin during even field display, and a low-level signal during odd field display. In TV sync mode, a high-level signal is input at the 2'') pin to display the even field, and a low-level signal to display the odd field.
Rev. 2.0, 09/02, page 81 of 366
When the ODEV bit is set to 1 in DSMR2, the polarity of the 2'') pin is the opposite of that described above. Figure 3.29 shows examples of raster scan control display. * Vertical scan synchronization example Non-interlace mode: 1/60 second/field, 1/30 second/field Interlace mode: 1/30 second/frame Interlace sync & video mode: 1/30 second/frame
00 01 02 03 04 05 06 07 08 09 Non-interlace mode 00 00 01 01 02 02 03 03 04 04 05 05 06 06 07 07 08 08 09 09 Interlace mode
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 Interlace sync & video mode Raster scanned in even field Raster scanned in odd field
Figure 3.29 Examples of Raster Scan Control Display
Rev. 2.0, 09/02, page 82 of 366
(2) Relationship with Monitor Display Method The methods for display monitor devices are largely divided into two types. * Interlace sync method In this method, the input image data for an odd and an even lines is switched at every scanning cycle VC. One image (a single frame) is thus composed for 2 VC (the first 1-VC data is persistence of vision). This method is common for TVs and VCRs.
Rev. 2.0, 09/02, page 83 of 366
* Display output (interlace) When the first field is an odd field and the second field is an even field, clear the ODEV bit to 0. (The odd and even fields belong to the same frame.) Odd field 0 1 2 3 238 239 Even field 0 1 2 3 238 239 * Display output (interlace sync & video) When the first field is an odd field and the second field is an even field, clear the ODEV bit to 0. (The odd and even fields belong to the same frame.) Odd field 1 3 5 7 477 479 Even field 0 2 4 6 476 478
When the first field is an even field and the second field is an odd field, set the ODEV bit to 1. (The odd and even fields belong to the same frame.) Even field 0 1 2 3 238 239 Odd field 0 1 2 3 238 239
When the first field is an even field and the second field is an odd field, clear the ODEV bit to 0. (The odd and even fields belong to the same frame.) Even field 0 2 4 6 476 478 Odd field 1 3 5 7 477 479
Figure 3.30 Display by Interlace Sync Method * Non-interlace method In this method, the input image data is displayed at a time without any intervals. Some highresolution monitors use this method.
Rev. 2.0, 09/02, page 84 of 366
* Display output (interlace) The ODEV bit and the not used.
signal are
0 1 2 3 4 5 6 7
476 477 478 479
Figure 3.31 Display by Non-Interlace Method Some display devices receive data in the interlace sync method and display the data in the non-interlace method (progressive conversion function). In this case, the first-half data stored in memory in the display device and the second half data are displayed at one time. Since the display is changed one time for 2 VC, clearness is increased, however, resolution is the same. Since a multi-scan monitor has a function for selecting the vertical scanning frequency of 55 to 160 Hz and the horizontal scanning frequency of 31 to 96 Hz, improvement of resolution can be achieved. Select an appropriate method of the Q2SD output to match the input method of the monitor used. Table 3.8 shows the possible combinations. Table 3.8 Combinations of Q2SD Output and Monitor Input Methods
Monitor Input Method Interlace sync Non-interlace Q2SD Non-Interlace Mode Blurring Available Q2SD Interlace Sync Mode Blurring Available Q2SD Interlace Sync & Video Mode Available Display size halved. Blurring
(1) Non-Interlace Mode Display The non-interlace mode is selected by setting the scan-mode bits in the display mode register (bits SCM1 and SCM0 in DSMR) to B00. In a non-interlace display, the display on the screen is updated at 59.94 frames/sec. This mode allows the display of high-quality images, since the speed of switching is high. The non-interlace mode is used to output images for non-interlace monitors.
Rev. 2.0, 09/02, page 85 of 366
The data read from the UGM as data for display includes the FG, BG, VW, cursor 1, and cursor 2, according to the settings in DSMR and DSMR2. The value of VID for the VW screen is checked on each field.
VSYNC UGM VID checked. Q2SD images (FB0, BG, and V0) are output. FB0
FB1
BG
VID checked. V0 Q2SD images (FB1, BG, and V1) are output.
V1
V2
Figure 3.32 Non-Interlace Mode Display Output
Rev. 2.0, 09/02, page 86 of 366
(4) Interlace Mode Interlace mode is entered by setting the scan-mode bits in the display mode register (bits SCM1 and SCM0 in DSMR) to B10. In interlace display driven by the Q2SD, the data output in each pair of an even and odd field is for the same frame. The display is at 29.97 frames/sec. and the screen switching speed is reduced. Since interlace mode is used to output to the interlaced display, the data read from the UGM includes the data for display as FG, BG, VW, cursor 1, and cursor 2, according to the settings in DSMR and DSMR2. VID of the VW screen is checked for each frame.
UGM VSYNC
FB0, BG, and V0 are output.
FB0
VID checked.
FB1
1 frame
BG
FB0, BG, and V0 are output.
VID not checked.
V0
V1
FB1, BG, and V1 are output.
V2
VID checked.
Figure 3.33 Interlace Mode Display Output
Rev. 2.0, 09/02, page 87 of 366
(5) Interlace Sync & Video Mode Interlace sync & video mode is entered by setting the scan-mode bits in the display mode register (bits SCM1 and SCM0 in DSMR) to B11. This mode is for output to an interlaced display. In the case for a television tuner, the data of a single frame is divided into an even and odd field while the Q2SD in interlace sync & video mode changes frames for every field. To achieve the correct composition of the window, select FB0 and FB1 which belong to one frame. Since the VID is updated every field, completely different fields may be composed. It is not a problem for still images, however, moving images are not displayed correctly. The display data in the Y direction only takes up half of the size set in DSY. VID on the VW screen is checked for each field.
UGM FB0 VSYNC
The even line data of FB0, BG, and V0 is output.
VID checked.
FB1 BG
V0
The odd line data of FB1, BG, and V1 is output.
VID checked.
1 frame
V1
V2
After 1/30 sec
FB0
The even line data of FB0, BG, and V2 is output.
VID checked.
FB1 BG
The odd line data of FB1, BG, and V0 is output.
VID checked.
1 frame
V0
V1
Different images are not composed.
V2
Figure 3.34 (1) Interlace Sync & Video Mode Output
Rev. 2.0, 09/02, page 88 of 366
UGM FB0
VSYNC
The even line data of FB0, BG, and V0 is output.
VID checked.
FB1 BG
V0
The odd line data of FB1, BG, and V1 is output.
VID checked.
1 frame
V1
V2
After 1/30 sec
FB0
The even line data of FB0, BG, and V2 is output.
VID checked.
FB1 BG
The odd line data of FB1, BG, and V0 is output.
VID checked.
1 frame
V0
V1
Different images are composed.
V2
Figure 3.34 (2) Interlace Sync & Video Mode Output
Rev. 2.0, 09/02, page 89 of 366
3.4.4
Synchronization Systems
The Q2SD is provided with a TV sync function in addition to master mode to simplify synchronization with an external device. The TVM (TV sync mode) bits in the display register (DSMR) are used to select master mode or TV sync mode. The frame and vertical blanking flags in the status register (the FRM and VBK flags in SR) are changed at detection of the vertical sync signal start position which is specified by the VSP bits in the vertical start position register (VSPR) regardless of sync mode. (1) Internal Synchronization Mode (Master Mode) Setting the horizontal and vertical sync signal (+6<1& and 96<1&) cycles and pulse widths in the display control register outputs the corresponding waveforms, and display data is output in synchronization with these signals. In interlace mode and interlace sync & video mode, a signal indicating odd field or even field is output at the 2'') pin. The UGM refreshing is performed on the basis of the +6<1& and 96<1& signals. (2) External Synchronization Mode (TV Sync Mode) In TV sync mode, the Q2SD is synchronized and operated using the horizontal and vertical sync signals of a TV, VCR, or other external system In this mode, the TV, video, or other system is treated as the master, and the Q2SD as the slave. Synchronization is performed every horizontal scan with the (;+6<1& input signal, and every vertical scan with the (;96<1& input signal. The Q2SD outputs display data on the basis of the falling edge of the (;+6<1& signal and the rising edge of the (;96<1& signal. In this mode, the horizontal sync signal, vertical sync signal, and clock from the sync signal generator should be input at the (;+6<1&, (;96<1&, and CLK1 pins, respectively. The &<6,1& pin outputs a high-level signal. Signals without equalizing pulses should be used for (;+6<1& and (;96<1&. In interlace mode and interlace sync & video mode, a signal indicating odd field or even field should be input at the 2'') pin. When the Q2SD is operated in TV sync mode, display control register HSWR, HCR, VSPR, and VCR settings are essential. In non-interlace mode, the 2'') pin should be fixed high or low to prevent an unstable input level at this pin.
Rev. 2.0, 09/02, page 90 of 366
The Q2SD performs UGM refreshing based on (;+6<1& and (;96<1&. Therefore, (;+6<1& and (;96<1& must be input to enable UGM refreshing to be carried out. The signal flow in TV sync mode is shown in figure 3.35. In this mode, the CDE pin can be controlled by the Q2SD by comparing the colors displayed by the Q2SD with the colors set in color detection registers H and L (CDERH, CDERL), and master R/G/B output and slave R/G/B output can be switched in pixel units by external circuitry. No matter whether display for the specified size in the Q2SD is completed or not, assertion of the (;96<1& signal makes the Q2SD process the vertical display completion operation and start the next screen display. When the (;96<1& signal is not asserted, the assertion of the signal is waited in the vertical blanking interval state (this is not automatically controlled). Similarly, assertion of the (;+6<1& signal makes the Q2SD process the horizontal display completion operation and start the next line display. When the (;+6<1& signal is not asserted, the assertion of the signal is waited in the horizontal blanking interval state (this is not automatically controlled).
TV (sync signal generator): master Clock Field signal R, G, B
CLK1 Q2SD: slave
R G B CDE
Input 2 Output Input 1
Display
CPU
UGM
Master R/G/B output (input 2) and slave R/G/B output (input 1) are switched by CED
Figure 3.35 Signal Flow in TV Sync Mode (3) TV Sync Mode Change Procedure When B'01 is set in the TV sync mode (TVM) bits in the display mode register (DSMR) and a transition is made to synchronization system switching mode, set the display reset bit (DRES) to 1 and clear the display enable bit (DEN) to 0 in the system control register before making the transition to synchronization system switching mode.
Rev. 2.0, 09/02, page 91 of 366
This procedure provides for the Q2SD to perform UGM refreshing in synchronization system switching mode. This procedure must only be carried out when the Q2SD is not performing drawing. The procedure is shown below. Steps 1 to 3 must be carried out in that order. 1. Set BG = 0, VWE = 0, CE1 = 0, and CE2 = 0. 2. Set DRES = 1 and DEN = 0. 3. Set TVM1 = 0 and TVM0 = 1. At this time, display reset is executed and the display buffer and the DBF flag is initialized to FB0 and 0, respectively. The procedure for switching from synchronization system switching mode to TV sync mode is shown in 4 to 7 below. 4. Input the clock to CLK1. When TVM1 = 1 and TVM0 = 0, also input signals to the (;+6<1&, (;96<1C, and 2'') pins. 5. If the display size is to be changed, set values in the Q2SD's address-mapped registers. 6. Set TVM1 = 0 and TVM0 = 0, or TVM1 = 1 and TVM0 = 0, to enable clock input from the CLK1 pin. If necessary, also set BG = 1, VWE = 1, CE1 = 1, and CE2 = 1. 7. Set DRES = 0 and DEN = 1. When an internal update is performed, the Q2SD begins display. The relationship between the display control register settings and the display signals is shown in figure 3.36.
Rev. 2.0, 09/02, page 92 of 366
HC HSW
VC VSP
(non-interlace operation)
DISP HDS HDE 1/2HC
Figure 3.36 Display Timing
Odd field
(interlace operation) Even field
Rev. 2.0, 09/02, page 93 of 366
(when ODEV = 0)
When performing display is master mode, the Q2SD outputs a composite sync signal. The signal waveform is based on the falling edge of 96<1&. The low-level width of equalizing pulses and separation pulses can be set in the equalizing pulse width register (EQWR) and the separation pulse width register (SPWR), respectively.
HC HSW
(non-interlace operation) (interlace, first half of frame) (CSY = 00) EQW (CSY = 10) Equalizing pulse: 3 rasters (CSY = 11) 1/2HC Equalizing pulse: 2.5 rasters Separation pulse: 2.5 rasters Equalizing pulse: 2.5 rasters Separation pulse: 3 rasters Equalizing pulse: 3 rasters SPW
(interlace, first half of frame) 1/2HC (CSY = 00) EQW (CSY = 10) Equalizing pulse: 3 rasters (CSY = 11) 1/2HC Equalizing pulse: 2.5 rasters Separation pulse: 2.5 rasters Equalizing pulse: 2.5 rasters Separation pulse: 3 rasters Equalizing pulse: 3 rasters SPW
Figure 3.37 3.4.5
&6<1& Output Waveform
Color Expansion of Display Screen
(1) Color Expansion of Display Screen The Q2SD incorporates the color palette function which can display 256 colors among 260,000 colors simultaneously. The R, G, and B have 6-bit configuration respectively, and are mapped to the Q2SD register space. The color palette function performs expansion of R, G, and B, which are six bits (260,000 colors), respectively, to the specified screen among foreground, background, or cursor screen in 8 bits/pixel. The color palette is shared among these screens.
Rev. 2.0, 09/02, page 94 of 366
(2) Color Expansion of Video Screen When the video screen is in the YCbCr format, the Q2SD performs expansion of the R, G, and B, each of 6 bits, (256,000 colors).
Rev. 2.0, 09/02, page 95 of 366
3.5
3.5.1
Rendering
Commands
The Q2SD performs drawing on the basis of a group of drawing commands located in the UGM. This group of drawing commands is called a display list. Drawing commands comprise fourvertex screen drawing and line drawing commands which draw at rendering coordinates, and work screen drawing and work line drawing commands which draw at work coordinates. As for drawing parameter setting commands, there are register setting command and sequence control commands which control the display list such as drawing end control. Line drawing, trapezoid fill, and current pointer setting commands include absolute coordinate and relative coordinate specification commands. Table 3.9 lists the drawing commands. Table 3.9
Type Four-vertex screen drawing
Drawing Commands
Command Name POLYGON4 Quadrilateral paint POLYGON4A POLYGON4B POLYGON4C Function Draws quadrilateral with four coordinates as vertices. Painting can be performed with source tiling and specified color. Four-vertex screen drawing with multi-valued source as transfer source Four-vertex screen drawing with binary source as transfer source Four-vertex screen drawing using specified color Draws solid polygonal line from start coordinates through nodal coordinates. Polygonal line drawing (absolute coordinate specification) Polygonal line drawing (relative coordinate specification)
Line drawing
LINE Polygonal line LINE RLINE
Draws polygonal line with line type (pattern) from start PLINE coordinates through nodal coordinates. Polygonal line with line-type specification PLINE RPLINE Pattern-reference polygonal line drawing (absolute coordinate specification) Pattern-reference polygonal line drawing (relative coordinate specification)
Rev. 2.0, 09/02, page 96 of 366
Table 3.9
Type Work screen drawing
Drawing Commands (cont)
Command Name FTRAP Trapezoid paint FTRAP RFTRAP CLRW Rectangle zero-clear Function Performs binary EOR painting of trapezoid with left side parallel to Y-axis. Binary EOR trapezoid fill (absolute coordinate specification) Binary EOR trapezoid fill (relative coordinate specification) Performs zero-painting of rectangle with diagonal designated by two coordinate points. Draws solid polygonal line from start coordinates through nodal coordinates. Binary polygonal line drawing (absolute coordinate specification) Binary polygonal line drawing (relative coordinate specification) Current pointer setting (absolute coordinate specification) Current pointer setting (relative coordinate specification) Local offset value setting (absolute coordinate specification) Local offset value setting (relative coordinate specification) Sets rectangle with diagonal designated by origin and specified coordinate point as clipping area. Sets rectangle with diagonal designated by two coordinate points as clipping area. Sets a specific address-mapped register. Command sequence jump (branch) Subroutine call (branch). Nesting depth is one. Subroutine return No operation: no processing executed. Waits until the next vertical blanking interval. Ends drawing processing and generates CPU interrupt.
Work line drawing
LINEW Polygonal line LINEW RLINEW
Register setting
MOVE RMOVE LCOFS RLCOFS SCLIP UCLIP WPR
Sequence control
JUMP GOSUB RET NOP3 VBKEM
Drawing end
TRAP
Rev. 2.0, 09/02, page 97 of 366
(a) 4-vertex drawing example
Reference
A
Drawing B
Source coordinates (b) Line drawing example B A Drawing C
C Rendering coordinates E Drawing D
D
F Rendering coordinates Rendering coordinates (c) Work drawing example (polygon) DXL Drawing A B F C E D Work coordinates (d) Work drawing example (line) A Work coordinates B Drawing C
Figure 3.38 Drawing Functions 3.5.2 Image Data Reference
The Q2SD can perform color-drawing while referring to the source data, or cutting-out drawing while referring to the work data. Among the Q2SD commands, the commands that refer to the source data are POLYGON4A, POLYGON4B, PLINE, and RPLINE. The commands that refer to the color data that is included in the command parameter are POLYGON4C, LINE, RLINE, LINEW, and RLINEW. Commands that refer to the binary-value work data are POLYGON4A, POLYGON4B, and POLYGON4C. The commands that create the binary work data are FTRAP, RFTRAP, LINEW, RLINEW, and CLRW. The reference to the binary work data can be performed simultaneously with the reference to the source data or the color data. There are two types of source data: multi-valued source data or binary source data.
Rev. 2.0, 09/02, page 98 of 366
Applicable command Transparent mode
POLYGON4A POLYGON4A
Multi-valued source data Specified color data Non-transparent mode
COLOR 0 COLOR 1 POLYGON4B POLYGON4B
Transparent mode
COLOR 1
Binary source data
POLYGON4B POLYGON4B
COLOR POLYGON4C POLYGON4C
Destination
Figure 3.39 Example of POLYGON4 Transfer Data Combinations (1) Multi-Valued Source Data Multi-valued source data is defined as multi-valued source coordinates (2-dimensional coordinates). However, the horizontal width (TDX) is specified as a value of 8 pixels or more. The configuration of multi-valued source data is shown in figure 3.40. In a linear arrangement (LNi = 1), a multiple of 8 pixels should be set as the TDX value. For the multi-valued source data, either 8 bits/pixel or 16 bits/pixel can be selected. When 8 bits/pixel is used, the lower bytes are the smaller side of the source coordinate x, and the higher bytes are the larger side of the source coordinate x.
Rev. 2.0, 09/02, page 99 of 366
TDX
X
Multi-valued coordinates
Y
Higher byte Lower byte
8-bit/pixel data
8-bit or 16-bit data
Figure 3.40 Multi-Valued Source Data Configuration (2) Binary Source Data Binary source data is arranged in linear fashion in the binary source area in the UGM, and is managed as 2-dimensional coordinates (binary source coordinates) by TDX and TDY in the POLYGON4B command. The left-hand screen pixel must be located at the LSB of the binary source data when the binary source data area is viewed from the Q2SD. However, the horizontal width (TDX) is specified as a multiple of 8 pixels. An example of binary source data is shown in figure 3.41. A binary source is used for the definition of character data and line-type data. When drawing, 0s are converted to COLOR0 data, and 1s to COLOR1 data (in transparent mode, only 1s are converted to COLOR1 data for drawing).
TDX LSB MSB LSB Example of kanji font as binary source TDX = 24, TDY = 24 Data: H'1C00, H'0E07, H'430C, H'0C1C, H'D8E3, H'FFFF, H'0C00, H'0003, H'030C, H'0140, H'4718, H'3FFF, H'636E, H'2C18, H'1863, H'6320, H'3018, H'1FFF, H'6310, H'1800, H'1860, H'FF98, H'0C3F, H'0060, H'600F, H'EC60, H'FFFF, H'B00C, H'0C01, H'0338, H'1C0C, H'0C0E, H'3C0E, H'038C, H'ECF8, H'6000
Binary source coordinates
Figure 3.41 Example of Kanji Font as Binary Source (TDX = 24, TDY = 24)
Rev. 2.0, 09/02, page 100 of 366
TDY
(3) Specified Color Data Specified color data is defined directly by drawing parameter color specifications (COLOR, COLOR0, COLOR1, LINE COLOR0, and LINE COLOR1). When the Q2SD is used for 8bit/pixel operation, the same color palette number is defined in the upper 8 bits and lower 8 bits in the drawing parameter color specification. When the Q2SD is used for 16-bit/pixel operation, the R, G, and B values are defined directly by the drawing parameter color specification. However, with LINEW and RLINEW, the value to be drawn at work coordinates is defined by the rendering attribute EOS bit. (4) Binary Work Data Binary work data is defined as binary work coordinates (2-dimensional coordinates). Work data is used to implement polygon painting. Polygon outline data is created with the FTRAP command, etc., and the created figure data is used to delineate the rendering figure. If, for example, the POLYGON4C command is used jointly for work, the work area polygon can be drawn in the rendering area with the specified color value. The configuration of binary work data is shown in figure 3.42.
Number of pixels specified by MWX bit (512/1023) X Binary work coordinates
Y LSB MSB
Figure 3.42 Binary Work Data Configuration 3.5.3 Rendering Attributes
Thirteen kinds of attribute specifications can be made: work (WORK), clipping (CLIP), transparent (TRNS), source style (STYL), net drawing (NET), source half (HALF), even/odd select (EOS), bold line drawing (FWUL, W2UL, FWDR, W2DR), source linear address (LNi), 4-pixel-unit processing (FST), source coordinate relative address (REL), edge (EDG), and color offset (COOF). The attributes that can be specified depend on the command. The rendering attributes are embedded in the commands, and can be specified on an individual command basis. Figure 3.43 shows the bit arrangement for rendering attributes.
Rev. 2.0, 09/02, page 101 of 366
15 CODE
11
10 DRAW MODE
0
POLYGON4A POLYGON4A POLYGON4B POLYGON4B POLYGON4C FTRAP, RFTRAP LINEW, RLINEW LINE, RLINE PLINE, RPLINE JUMP, GOSUB CLRW
(Commands other than the above)
TRNS STYL CLIP TRNS STYL CLIP TRNS STYL CLIP TRNS 0 CLIP CLIP CLIP CLIP CLIP TRNS 1 CLIP
0 REL REL REL
NET NET NET NET NET
EOS EOS EOS EOS EOS EOS
FST 0
LNi COOF WORK 1 COOF WORK WORK 0 HALF WORK WORK
FST EDG
NET NET REL
EOS EOS FWUL W2UL FWDR W2DR EOS EDG2 EDG1 1
CLIP
Note: Shaded areas should be cleared to 0. FWUL, W2UL, FWDR, W2DR: Bold line drawing bits REL: Relative address specification EDG: Edge drawing bit
Figure 3.43 Rendering Attribute Bit Arrangement (1) Transparency Specification (TRNS) When color expansion of binary source data is performed, transparency or non-transparency can be selected on an individual drawing command basis with the TRNS bit. When transparency is selected, a 0 in the binary source data is transparent and a 1 has the value of the COLOR1 parameter. When non-transparency is selected, a binary data 0 has the value of the COLOR0 parameter, and a 1 has the value of the COLOR1 parameter. With multi-valued source data, all-0 data becomes a transparent color, and those pixels are not drawn. The transparency specification can be used with the POLYGON4A, POLYGON4B, PLINE, and RPLINE commands; in other commands, the TRNS bit should be cleared to 0. (2) Source Style Specification (STYL) When drawing a rectangle, the STYL bit can be used to select, on an individual drawing command basis, whether the source data is to be enlarged or reduced, or referenced repeatedly. If no style specification is made, the source data is enlarged or reduced in proportion to the size of the rendering area. When a style specification is made, the source data is referenced repeatedly in proportion to the size of the rendering area. This attribute is therefore used when drawing repeated patterns such as hatch patterns. The source style specification can be used with the POLYGON4A, POLYGON4B, PLINE, and RPLINE commands; in other commands, the STYL bit should be cleared to 0. When a source style specification is used, do not make a source half specification. An example of a source style specification is shown in figure 3.44.
Rev. 2.0, 09/02, page 102 of 366
No style specification (STYL = 0)
Example of enlarged by factor of 2
Style specification used (STYL = 1)
Referenced twice Source data Drawing data
Figure 3.44 Example of Source Style Specification (3) Clipping Specification (CLIP) The Q2SD can perform clipping area management. In the clipping area, drawing is performed. Outside the clipping area, only operations are performed although the results are not written to memory. There are two kinds of clipping area: a system clipping area designated by the SCLIP command, and a user clipping area designated by the UCLIP command. The system clipping area has a fixed drawing range. The system clipping area is always valid, regardless of attribute specifications. A user clipping area can be designated as desired within the system clipping area. Whether or not clipping is performed in that area can be selected on an individual command basis with the rendering attribute CLIP bit. The boundary is drawn. Clipping is set in the screen coordinates without offset. Figure 3.45 shows an example of the clipping specification.
Rev. 2.0, 09/02, page 103 of 366
An example of a clipping specification is shown in figure 3.42.
(0, 0)
CLIP bit = 1 CLIP bit = 0
System clipping area
Designated user clipping area (359,239) Rendering coordinates without offset Work coordinates without offset
Figure 3.45 Example of Clipping Specification (4) Net Drawing Specification (NET) The NET bit can be used to select, on an individual drawing command basis, whether or not net drawing is to be performed. Net drawing is a function for drawing only pixels at coordinates for which the condition "rendering coordinates X + Y = EOS (0: even number, 1: odd number)" is true. For example, if EOS = 0, drawing will only be performed at coordinates Y = 0, X = 0, 2, 4, 6, 8, ..., Y = 1, X = 1, 3, 5, 7, 9, ... . This function enables the drawn figure and ground to be mutually semi-composed. The net drawing specification can be used with the POLYGON4 commands, and the LINE, RLINE, PLINE, and RPLINE commands; in other commands, the NET bit should be cleared to 0. (5) Even/Odd Select Specification (EOS) Even pixels are selected when EOS = 0, and odd pixels when EOS = 1. The even/odd select specification is used together with the net specification or source half specification. With the LINEW and RLINEW commands, drawing is performed at the work coordinates with 0 when EOS = 0, and with 1 when EOS = 1. Examples of even/odd select specifications are shown in figure 3.46.
Rev. 2.0, 09/02, page 104 of 366
Even-number referencing with half drawing specification (HALF = 1, EOS = 0)
Odd-number referencing with half drawing specification (HALF = 1, EOS = 1)
Starting point
Source data
Drawing data
Figure 3.46 Examples of Even/Odd Select Specifications (6) Source Half Drawing Specification (HALF) The HALF bit can be used to select whether all or only half of the source data is to be referenced. When the source half drawing specification is selected, only EOS (0: even number, 1: odd number) data is referenced from the source starting point. Thus only half of the source data in the horizontal direction is referenced. The source half drawing specification can only be used with the POLYGON4B (binary source) command; in other commands, the HALF bit should be cleared to 0. When a source half specification is used, do not make a source style specification. Do not use this specification when the x coordinate of the drawing coordinates is within a negative range since the drawing image may be distorted. (7) Work Specification (WORK) When drawing is performed at rendering coordinates with POLYGON4 commands, the WORK bit can be used to select, on an individual drawing command basis, whether or not binary work data is to be referenced. When binary work data referencing is selected, drawing is performed if the work data for the pixel corresponding to the rendering coordinates is 1, but not if the work data is 0. The same shape as that drawn at work coordinates can thus be drawn at rendering coordinates. Drawing at work coordinates can be performed either by means of the FTRAP command or else by the SuperH. Ensure that UGM drawing access by command and UGM drawing access by the SuperH are not performed simultaneously. The work specification can be used with the POLYGON4A, POLYGON4B, and POLYGON4C commands; in other commands, the WORK bit should be cleared to 0. With the PLINE and RPLINE commands, this attribute is specified but work references are not performed.
Rev. 2.0, 09/02, page 105 of 366
(8) Bold Line Drawing Specification Taking individual line segments of a polygonal line specified by parameters as reference lines, this specification makes the reference lines bold lines in the upper-left direction and lower-right direction, independently. Whether or not this attribute is enabled is specified by the FWUL bit and FWDR bit, while the width of a bold lines can be selected from line widths 1 to 5 by a combination of bits W2UL and W2DR. The FWUL bit enables bold-line implementation in the upper-left direction, while the FWDR bit enables bold-line implementation in the lower-right direction. The W2UL bit is valid when FWUL = 1, and the W2DR bit when FWDR = 1. This function is valid for each segment of a polygonal line. Using the segment line main scanning axes, lines with the same slope in the up (left) and down (right) directions, and of the same length, are drawn repeatedly. Therefore, the shape of the segment linkage parts is not considered. This function can be used with the LINE and RLINE commands; in other commands, the FWUL, W2UL, FWDR, and W2DR bits should all be cleared to 0. When performing bold line drawing, set the vertex coordinates so that the entire bold line area does not extend beyond the drawing area (both x and y in the range -2045 to 2044). Table 3.10 Bold Line Drawing Settings
FWUL 0 W2UL 0 FWDR 0 1 1 0 1 1 0 0 1 1 0 1 W2DR 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Line Width (Direction, Magnification) 1 (no magnification) 1 (no magnification) 2 (lower right 1) 3 (lower right 2) 1 (no magnification) 1 (no magnification) 2 (lower right 1) 3 (lower right 2) 2 (upper left 1) 2 (upper left 1) 3 (upper left 1, lower right 1) 4 (upper left 1, lower right 2) 3 (upper left 2) 3 (upper left 2) 4 (upper left 2, lower right 1) 5 (upper left 2, lower right 2)
Rev. 2.0, 09/02, page 106 of 366
1. Upper-left magnification 1 (W2UL = 0), lower-right magnification 2 (W2DR = 1)
Reference line dy dy
dx dx (a) When dx dy (b) When dx < dy
2. Upper-left magnification 2 (W2UL = 1), lower-right magnification 1 (W2DR = 0)
dy dy
dx dx (a) When dx dy (b) When dx < dy
Figure 3.47 Examples of Bold Line Drawing (9) Source Address Linear Specification (LNi) Use of a 2-dimensional virtual address or a linear address as the source address can be selected, on an individual drawing command basis, by means of the LNi bit. To use a linear address, set this bit to 1. This function can be used with the POLYGON4A command; in other commands, the LNi bit should be cleared to 0. For details of command operation, see section 4.1.1, POLYGON4A. (10) 4-Pixel-Unit Processing (FST) Whether or not 4-pixel unit processing is performed can be specified for individual drawing commands by means of the FST bit. To perform 4-pixel unit processing, set the FST bit to 1. In this case, no other rendering attributes except CLIP can be used. This function can be used with the POLYGON4A and POLYGON4C commands; in other commands, the FST bit should be cleared to 0.
Rev. 2.0, 09/02, page 107 of 366
When using this attribute, set the command parameters as indicated in the individual command descriptions. (11) Source Coordinate Relative Address Specification (REL) Setting the REL bit to 1 in POLYGON4A, POLYGON4B, JUMP, and GOSUB commands enables source referencing and branching to be performed at an address relative to (before or after) the command code. The source address must be a linear address. Also, for reasons relating to referencing of a multi-valued source arranged in linear fashion, the LNi bit must be set to 1 when using POLYGON4A; operation cannot be guaranteed if the LNi bit is 0. The command code address is the relative address origin. (12) Edge Drawing (EDG) With the FTRAP and RFTRAP commands, setting the EDG bit to 1 enables edge lines to be drawn after completion of trapezoid painting. Whether edge line drawing is performed with 0 or with 1 is specified by the EOS bit. (13) Line Drawing Edge Specification (EDG1, EDG2) Whether or not edge drawing is performed for a polygonal line with line type can be specified for individual drawing commands by means of the EDG1 bit. This function is valid for each segment of a polygonal line. Using the segment line main scanning axes, solid lines with the same slope and of the same length, are drawn either vertically or horizontally. Therefore, the shape of the polygonal line linkage parts is not considered. The solid edge lines have the value of COLOR1. This function can be used with the PLINE and RPLINE commands; in other commands, the EDG1 bit should be cleared to 0. A source size of 8 or 16 can be used. Set 8 or 16 for source size parameter TDX.
Rev. 2.0, 09/02, page 108 of 366
Edge drawing 1 specification (EDG1 = 1) Reference line
X-axis main scan drawing
Y-axis main scan drawing
Whether or not edge drawing is performed for a polygonal line with line type can be specified for individual drawing commands by means of the EDG2 bit. This function is valid for each segment of a polygonal line. Here, each segment of the polygonal line specified by the parameter is considered as a reference line. This function is implemented for each segment of a polygonal line, using the following procedure. First, the reference line is drawn as a line with line type. Next, using the segment line main scanning axes, solid lines with the same slope and of the same length, are drawn either vertically or horizontally. Finally, the reference line is drawn as a solid line. Therefore, the shape of the polygonal line linkage parts is not considered. The solid line drawn last has the value of COLOR1. This function can be used with the PLINE and RPLINE commands; in other commands, the EDG2 bit should be cleared to 0.
Edge drawing 2 specification (EDG2 = 1) Reference line
X-axis main scan drawing
Y-axis main scan drawing
Rev. 2.0, 09/02, page 109 of 366
Both the EDG1 and EDG2 bits should not be set to 1 at the same time. (14) Color Offset (COOF) This function can be used with the POLYGON4A command. In 16-bit/pixel drawing, if the rendering attribute COOF bit is set to 1, the result of adding the value in the COLOR register to the value of the multi-valued source data is drawn. The operation is performed by saturation processing. In 8-bit/pixel drawing, the COOF bit must be cleared to 0. Use 100% or enlarged drawing since miniaturized drawing of the source may distort the image. 3.5.4 Command Fetching
(1) Command Fetch Operation When the rendering start bit RS in the system control register SYSR is set to 1, the Q2SD fetches the display list in the UGM to carry out drawing operations. The display list and the source data to be used by the display list should be stored in the UGM before the Q2SD starts to fetch the display list by the rendering start bit. The Q2SD performs sequential fetches in low-to-high address order, starting at the address set in the display list start address register (DLSAR). The fetch address can be changed midway, using a JUMP or GOSUB command. Q2SD fetching can be terminated by placing a TRAP command at the end of the display list. The Q2SD has a dedicated command buffer, and an equivalent area of the UGM is accessed at one time. When processing of the commands in this buffer is completed, another command fetch is performed. If the commands include a JUMP, GOSUB, or other command that changes the flow, the Q2SD starts fetching again from the new address indicated by that command. Figure 3.48 shows an example of the display list.
Rev. 2.0, 09/02, page 110 of 366
DLSAR
Command sequence 1
JUMP
Command sequence 2 GOSUB
Subroutine RET (Subroutine depth is limited to one level)
TRAP
Figure 3.48 Example of Display List (2) Drawing Suspension and Resumption The Q2SD supports a drawing suspend/resume function, synchronized with the 96<1& signal between the CPU and Q2SD. This enables multiple drawing processing to be performed in parallel with priority order. This function is mainly used when alternately using frame buffers and the background screen to execute drawing.
Rev. 2.0, 09/02, page 111 of 366
Frame buffer drawing Q2SD drawing processing
Interrupt generated by Q2SD Background screen drawing
Interrupt generated by Q2SD Background screen drawing
VBK = 1 RBRK = 1 BRK = 1
RS = 1
TRA = 1 Interrupt acceptance
Drawing suspension command
CPU processing
Interrupt acceptance
Figure 3.49 Example of Timing for Suspending and Resuming Background Screen Drawing (3) Suspension Processing 1. Set BRCL to 1 in the status clear register (SRCR), clear the BRK bit to 0 in the status register (SR), and set the drawing suspension directive bit (Rendering Break: RBRK) to 1 in the system control register (SYSR). 2. Next, monitor the BRK bit and TRA bit. 3. When BRK is observed to be set to 1, this means that the currently executing drawing command processing has ended and the drawing unit has halted (drawing has been suspended) at the point at which the next drawing command was fetched. Information required for software processing in anticipation of resumption processing should be read from the address-mapped registers and saved in memory. At this time, the RBRK bit is cleared to 0. 4. When TRA is observed to be set to 1, this means that a TRAP command has been executed and Q2SD drawing processing has ended. Therefore, ensure that no subsequent resumption processing is carried out. If drawing is to be performed after suspension processing, wait until the TRA flag is observed to be set to 1.
Rev. 2.0, 09/02, page 112 of 366
Drawing resumption
Interrupt drawing
RS = 1
(4) Resumption Processing 1. The parameters saved immediately after suspension are restored. Some are written directly to the registers, and some are set by command. The former include the subroutine return address (which can also be set with the WPR command), and the latter, clip area, local offset, current pointer, and execution restart addresses. Of the latter, the execution restart address is restored by setting the command status register value at the time of the suspension as the jump destination of a JUMP command. For the other parameters in the latter group, settings should be made to provide for recovery by means of the appropriate command before execution of this JUMP command. 2. After performing a write for the purpose of subroutine return address restoration, and creating a command list to restore the other parameters, drawing can be resumed by setting the address of this command list in DLSAR and implementing a rendering start. 3.5.5 Internal Buffer
The Q2SD has three internal buffers--a command buffer, source buffer, and work buffer--as shown in figure 3.50.
UGM
Q2SD
Display list
Command buffer size Command buffer size
A B
Command buffer AB
Binary source coordinates or multi-valued source coordinates
Source buffer size Source buffer size
C D
Source buffer CD
Binary work coordinates
Work buffer size Work buffer size
E F
Work buffer EF
Figure 3.50 Updating of Q2SD's Internal Buffers
Rev. 2.0, 09/02, page 113 of 366
These buffers are used by the Q2SD to temporarily store data held in the UGM. The Q2SD uses the data stored in these buffers when executing drawing. The functions of these buffers are as follows: 1. Command buffer (32 bytes x 2) Used by the Q2SD to store a display list held in the UGM. The buffer size is 64 bytes. 2. Source buffer (64 bytes) Used by the Q2SD to store a binary source or multi-valued source held in the UGM. The buffer size is 64 bytes. 3. Work buffer (16 bytes) Used by the Q2SD when performing drawing at binary work coordinates in the UGM. The buffer size is 16 bytes. When buffer contents are not updated, (when the same address is referenced by data of or below the capacity of the buffer, or a reference ends at a location at or below the capacity of the buffer from the previous reference start location), the previous buffer contents will be used even though the data in the UGM is rewritten. To intentionally update buffer contents, the address of a location exceeding the buffer capacity should be referenced.
3.6
Video Capture
The Q2SD can incorporate a YUV 4:2:2 8-bit data stream obtained by digital encoding of NTSC signals. The captured data is displayed on the video screens. 3.6.1 Configuring Circuit for Video Capture
(1) Video Capture Operation Video capture is performed at the rising edge of the VQCLK signal. The 8-bit data stream corresponding to the number of pixels set in the VSIZEX field in the video window size register (VSIZER) is captured for each VHS signal and transferred to one of three video storage areas determined by video area start address registers (VSAR). These areas are used sequentially in frame units. The video window status bits (VID0, VID1) are valid when 0 is set in the video incorporation enable bit (VIE) and indicate the most recent video area in which video capture has been completed. The size of the video storage areas is determined by VSIZEX and VSIZEY. Use a frequency not exceeding 1/2 the system operating clock frequency for VQCLK (the system operating clock should be in the range 64 to 66 MHz). A number of VQCLK cycles equal to twice the number of luminous pixels are necessary per VHS. 996, 9+6, 92'' and VQCLK are accepted following hardware reset release, and video capture is started by setting VIE to 1, having the first VVS signal sync signal input, then having the first VHS signal sync signal input.
Rev. 2.0, 09/02, page 114 of 366
As the video storage area capture line number is incremented each time a VHS signal sync signal is input, VQCLK must not be input during the VHS signal sync signal period. The VQCLK pin should be low level except when a valid data is output. For video capture, select a UGM bus width of 32 bits by setting MES1 and MES0 in the memory mode register (MEMR). The relationship between video input signals is shown in figures 3.51 and 3.52.
VIN7 to VIN0 VQCLK
VVS VHS
VODD (FIELD)
QCLK
VD[15:8]
,,,,,,,,,,, ,,,,,,,,,,, ,, ,,,,,,,,,,
tVHS -2H -1H tVOS 1/ 2 3/ 4 5/ 6 7/ 8 9/ 10 11/ 12 13/ 14 Synchronization period The VQCLK signal should not be input during this period. tHQS Capture is possible. (VQCLK)
(2) Video Capture and Display Operation

,
Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr2 Y3
Figure 3.51 Video Incorporation Signals
Figure 3.52 Video Capture Timing
As the data (which supports to the 8-bit YCbCr (2:2:1) format specified in ITU-601) arrives from the video decoder, the video-capture function writes it to the video-capture area in the UGM. Three areas, V0, V1, and V2, are captured in the order and video display from an area may commence once the operation of writing to that area has been completed.
Rev. 2.0, 09/02, page 115 of 366
V0
V1
V2
The current area for writing is automatically switched when the capture of data for one area has been completed. Capture
V0 V1 V2 V0 V1 V2 V0
Display
V0
V1
V2
V0
V1
V2
V0
Figure 3.53 Capture State The functions of displaying and capturing video data are each capable of independent operation since the Q2SD is able to capture video data whether the display is on or off; that is,. Using the three areas makes it possible to deal with the situation where the times at which capture and display start are not synchronized and thus do not necessarily match. While video capture is in progress (VIE = 1), display of the area specified by the immediately prior value of the VID bits commences. When a capture operation stops while it is in progress, the current screen continues to be displayed, as is shown in figure 3.54. When the capture operation is resumed, the current screen will continue to be displayed until the VID bits are updated on completion of the capture of one screen. Setting the VIE bit to 1 resets the video capture area to V0.
Capture stopped Updating VID V0 V1 V2 V0 V1
Capture
00
01
10
,
00 V2
Capture resumed
. . . . . . . .V0 . . . .V1 . . . . . . . . . . . . . . . . . . . . . . . . .00 . . . .01 . . . . . . . . . .V0 . . . . . . . . V0 . . . V0 . . . . . . . . .. .. V0
Display
V0
V1
Figure 3.54 Display State 3.6.2 Video Capture Mode
The mode of capture by the Q2SD is selectable from among four modes. The appropriate mode is selected by such factors as the resolution of the video screen, the output format of the video decoder, and the destination device (CRT, LCD, TV, etc.) for the output signal.
Rev. 2.0, 09/02, page 116 of 366
When ODEN1, ODEN0 = 0, 1, a one-frame screen is created by combining even and odd fields. Motion interpolation is not performed. In the case of moving pictures with violent motion, the screen may be difficult to see as a still picture. This mode is suitable for interlace display under conditions in which the frame rate and the number of scanning lines in the vertical direction are both the same as for the input video. Line 1 is line 0 of the UGM to support the case that the original signal has no line 0. Note that even and odd lines are reversed between the original signal and the UGM. Therefore, capture begins with an odd field (VINM = 0) when an even field is displayed first within a frame (ODEV = 1), and with an even field (VINM = 1) when an odd field is displayed first within a frame (ODEV = 0). When ODEN1, ODEN0 = 1, 0, or 1, 1, a one-field image is treated as a one-field image. At this time, the number of vertical scanning lines is halved. Original-size display is not possible. To preserve the vertical/horizontal ratio, the horizontal multiplication factor should be adjusted. This mode is used for non-interlace (SCM1, 0 = 0:0) display. Set the value of VACTIVE according to the setting of ODEN1 and ODEN0 in the video incorporation mode register (VIMR). When performing video capture, input the video stream data to the VIN pin, without having scaling processing (thinning-out processing) performed by the video stream decoder. 1. When ODEN1 = 0 and ODEN0 = 1 Make the value of VACTIVE the total number of effective display lines in the vertical direction in two 2 996 intervals. For example, with 240 effective display lines in the vertical direction in one 1 996 interval, the setting should be: VACTIVE = 240 x 2 = 480 2. For settings other than ODEN1 = 0, ODEN0 = 1 Make the value of VACTIVE the number of effective display lines in the vertical direction in one 1 996 interval.
Rev. 2.0, 09/02, page 117 of 366
HACTIVE
VACTIVE
Video data display size
Video stream decoder
Q2SD VQCLK VIN7-VIN0
UGM
VSIZEY
Video screen area
VSIZEX
VSIZEX: Horizontal reduction (thinning-out) ratio set by video incorporation reduction ratio (1/1, 1/2, 1/3, 1/4, or 1/6) VSIZEY: Vertical reduction (thinning-out) ratio set by video incorporation reduction ratio (1/1, 1/2, 1/3, or 1/4) HACTIVE (pixels) VSIZEX VACTIVE (pixels) VSIZEY VQCLK high-level width (sec.) 2 MCLK
MCLK = CLK0 x N (Hz) CLK0: Frequency (Hz) of clock input to CLK0 pin N: Multiplication factor determined by pins MODE2 to MODE0
Figure 3.55 Video Screen Area (3) Non-Interlace Mode Capture (ODEN1 = 0, ODEN0 = 0) This is the appropriate mode when the video decoder is in non-interlace mode. All video data for each VSYNC signal is stored in a single capture area. When the output of the video decoder is in interlace sync mode, take care with regard to the size of the capture area taken up by the captured data, since the data consists of only half of the lines for the screen.
Rev. 2.0, 09/02, page 118 of 366
Video decoder output
Capture area
V0
V1
V2
Figure 3.56 Interlace Capture (4) Interlace Composite Capture (ODEN1 = 0, ODEN0 = 0) This mode is applicable to video data for an interlaced display. Data for the odd and even fields are composed and stored in a single capture area. When the signal output by the video decoder is not for an interlaced display, correct operation is not guaranteed.
Even field
Odd field
Video decoder output
Composite Capture area V0 V0 V1
Figure 3.57 Interlace Composite Capture (5) Interlace Capture (Odd Field Only: ODEN1 = 1, ODEN0 = 0) This stores the odd fields of data for an interlaced mode display (the VODD signal is at its low level) in a single capture area. Take care with regard to the size of the capture area taken up by the captured data, since the data consists of only half of the lines for the screen. When the output of the video decoder is in non-interlace sync mode, every second field of data will not be stored. The data size for capture, however, are the same.
Rev. 2.0, 09/02, page 119 of 366
Odd field
Video decoder output
This field is not captured.
This field is not captured.
Capture area
V0
Figure 3.58 Interlace Capture (Odd Field) (6) Interlace Capture (Even Field Only: ODEN1 = 1, ODEN = 1) This stores the even fields of data for an interlaced mode display (the VODD signal is at high low level) in the capture area. Take care with regard to the size of the capture area taken up by the captured data, since the data consists of only half of the lines for the screen. When the output of the video decoder is in non-interlace sync mode, every second field of data will not be stored. The data size for capture, however, are the same.
Even field
Even field
Video decoder output
This field is not captured.
Capture area
V0
V1
Figure 3.59 Interlace Capture (Even Field) (7) Field Order for Video Capture The field order for video capture is specifiable by the video incorporation mode bit (VINM) in the video incorporation mode register (VIMR). This enables to assign the first field to either the
Rev. 2.0, 09/02, page 120 of 366
upper or lower line. Motion interpolation is not performed. In the case of moving pictures with violent motion, the screen may be difficult to see as a still picture.
* Video input decoder (video decoder output) When the first field is an odd field and the second field is an even field, clear the VIMM bit to 0. (The odd and even fields belong to the same frame.)
When the first field is an even field and the second field is an odd field, set the VIMM bit to 1. (The odd and even fields belong to the same frame.)
1 3 5 7 477 479 0 2 4 6 476 478
0 2 4 6 476 478 1 3 5 7 477 479
Video capture * Video area (UGM) When ODEN1 = 0 and ODEN0 = 1 (composite and capture), the first field is stored in an even line and the second field is stored in an odd line.
0 1 2 3 4 5 6 7 1 0 3 2 5 4 7 6
Video capture When ODEN1 = 0 and ODEN0 = 1 (composite and capture), the first field is stored in an even line and the second field is stored in an odd line.
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
476 477 477 478 479 479
478 478
476 476 477 478 478 479
477 479
When ODEN1 = 1 and ODEN0 = 0 (odd field capture), odd fields (first field) are stored sequencially.
0 1 2 3 1 3 5 7
When ODEN1 = 1 and ODEN0 = 0 (odd field capture), odd fields (second field) are stored sequencially.
0 1 2 3 238 239 1 3 5 7 477 479
238 477 239 479
When ODEN1 = 1 and ODEN0 = 0 (even field capture), even fields (second field) are stored sequencially.
0 1 2 3 238 239 0 2 4 6 476 478
When ODEN1 = 1 and ODEN0 = 0 (even field capture), even fields (first field) are stored sequencially.
0 1 2 3 0 2 4 6
238 476 239 478
Figure 3.60 Interlace Video Input Field Handling Specification
Rev. 2.0, 09/02, page 121 of 366
3.6.3
Reduction of Video Capture Images
The size of the captured image may be reduced by setting bits VSIZ0 to VSIZ4 in the video capture mode register (VIMR), where vertical and horizontal reduction ratios are independently specifiable. The selectable reduction ratios in the horizontal direction are 1/2, 1/3, and 1/4 and the ratios in the vertical direction are 1/2, 1/3, and 1/4. The VSIZEX and VSIZEY bits should be set to the value obtained that the number of horizontal/vertical valid pixels is multiplied by the video incorporation reduction ratio (VSIZ4 to VSIZ0) and the result is rounded down to 0.
1/6 1/4 1/3 106 160 212 1/2 320 VSIZEX 640
1
1
1/4 120 1/3 160 1/2 240
VSIZEY 480 When data of 640 x 480 is captured from a video decoder
Figure 3.61 Reducing the Size of the Captured Image As an example, when the setting of the VSIZEX bits is 480 and the setting for the reduction ratios is as above, each current frame of data in the memory is displayed on a video-screen area which is wider than 320 pixels since video data is not sent for the horizontal pixel range from 321 to 480. On the other hand, when the setting of the VSIZEX bits is 240, which is smaller than the captured image, the data which is displayed will be cut off since there is no screen area for the horizontal pixel range from 241 to 320.
Rev. 2.0, 09/02, page 122 of 366
320
480
240 320
240
The system attempts to display data which is not being captured (the corresponding current area is displayed).
200 240
480
The data of this area is not captured. When horizontal and vertical reduction ratios of 1/2 are set for 640 x 480 pixel data and the respective settings for the VSIZEX and VSIZEY bits are 240 and 200
When horizontal and vertical reduction ratios of 1/2 are set for 640 x 480 pixel data and both the VSIZEX and VSIZEY bits are set to 480
Figure 3.62 Incorrect Settings for the Reduction Ratios These failures will occur with incorrect setting of the VSIZEY bits. When the result of a reduction calculation is non-integer or odd, the result is rounded off to obtain an even number. Example: Size of data to be sent by video decoder x reduction ratio = video window size X: 640 x 1/3 = 213.3333 212 Y: 480 x 1/3 = 160 3.6.4 Setting Video Capture Position
The method of address calculation is shown below.
Rev. 2.0, 09/02, page 123 of 366
Coordinates when MWX = 0 (512) VSAH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000
VSAL 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 000000000
12 11 10 9 8 7 6 5 4 3 2 1 0 Y coordinate 0 0 0 0 X coordinate
9876543210 00000
Coordinates when MWX = 1 (1024) VSAH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000000
VSAL 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 000000000
11 10 9 8 7 6 5 4 3 2 1 0 Y coordinate 0 0 0 0 X coordinate
10 9 8 7 6 5 4 3 2 1 0 00000
Figure 3.63 Setting up the Capture Area Within the range of the UGM, any multiple of 16 is specifiable as the Y coordinate and any multiple of 64 is specifiable as the X coordinate. Note that the specified area is accessed as 16bit/pixel data. Therefore, when the video screen overlaps with the foreground or background screen, the area of overlap is also accessed as 16-bit/pixel data. When the MWX bit is specified as 0 to select the 512-pixel mode, the values for the Y coordinate are from 0 to 8176 (pay attention to the setting for memory) and values for the X coordinate are from 0 to 960 (actually, the values which exceeds 511 should not be specified); Y coordinates are specified as integer multiples of 16 and X coordinates are specified as integer multiples of 64. When the MWX bit is specified as 1 to select the 1024-pixel mode, the values for the Y coordinate are from 0 to 4080 and the values for the X coordinate are from 0 to 1984 (actually, values which exceed 1023 should not be specified); Y coordinates are specified as integer multiples of 16 and X coordinates are specified as integer multiples of 64. The value of the video window size in the X direction (VSIZEX) is up to 640. An example of the calculation of the video area is given below. When the MWX bit specifies 512-pixel mode and three video screens are allocated, as is shown in figure 3.64, the settings of each of VSAH and VSAL registers are as given below.
Rev. 2.0, 09/02, page 124 of 366
0 V0 112 119 208 231 327
119128
247256
375 511
V1
V2
FG
BG
Figure 3.64 Example of the Settings for Capture Areas V0: X = 0, Y = 0 Y coordinate: 0000000000000, X coordinate: 00000000000 VSA: 0000000000000000, 0000000000000000 VSAH0: H0000, VSAL0: H0000 V0: X = 128, Y = 112 Y coordinate: 0000001110000, X coordinate: 00010000000 VSA: 0000000000000001, 1100010000000000 VSAH0: H0001, VSAL0: HC400 V0: X = 256, Y = 208 Y coordinate: 0000011010000, X coordinate: 00100000000 VSA: 0000000000000011, 0100100000000000 VSAH0: H0003, VSAL0: H4100 3.6.5 Format of Captured Data
The Q2SD video input interface supports the 8-bit YCrCb pixel-stream format. Table 3.11 shows the configuration of the Q2SD's pins and the correspondence between the Q2SD pins and the bits of Y, Cr, and Cb data. Figure 3.65 shows the flow of data from a video decoder. A video signal according to the NTSC specification consists of the Y, or luminance, signal (monochrome signal) and the C, or chrominance, signal (color signal)--this was chosen to retain compatibility with monochrome broadcasting. The result of the sampling of these signals by a video decoder is the quantized data.
Rev. 2.0, 09/02, page 125 of 366
Since the NTSC specification is based on the nature of the human eye, which is less sensitive to chrominance than to luminance, chrominance is only represented by half as many bits as luminance. Only half as many bits are thus sampled from the C signal as from the Y signal, and the same proportion applies to the data. Furthermore, the C data is also divided into red and blue components, i.e., Cr (red - Y) and Cb (blue - Y). The final result is thus YCbCr data. Figure 3.66 depicts the data for one pixel. Table 3.11 8-Bit Pixel Interface
Q2SD Y data C data VIN7 Y7 Cr7 Cb7 VIN6 Y6 Cr6 Cb6 VIN5 Y5 Cr5 Cb5 VIN4 Y4 Cr4 Cb4 VIN3 Y3 Cr3 Cb3 VIN2 Y2 Cr2 Cb2 VIN1 Y1 Cr1 Cb1 VIN0 Y0 Cr0 Cb0
15 Image data (1st word) Y0
87 Cb0
0
Image data (2nd word)
Y1
Cr0
Image data (3rd word)
Y2
Cb2
Data flow
Image data (4th word)
Y3
Cr2
Image data (nth word) n = Even number
Yn-1
Crn/4
Figure 3.65 The Flow of YCbCr (4:2:2) Data
Rev. 2.0, 09/02, page 126 of 366
1 pixel Y: 8 bits Cb: 8 bits Cr: 8 bits
1 pixel Y: 8 bits
Two pixels of data are processed as a single item of information in the YCbCr format. One pixel of data consists of the components shown below. 1 pixel = Y (8 bits) + Cb (4 bits) + Cr (4 bits) = 16 bits The ration of the respective amounts of data is thus 2:1:1. Since two pixels of data are sent in each transmission as described above, the ratio is in fact 4:2:2.
Figure 3.66 YCbCr (4:2:2) Data Format Although YUV and YC data differ in terms of the range used to represent the data (notation), the same formula, which conforms with CCIR-601, is applied in converting both into RGB format. YUV data is represented by values in the range from 0 to 1 while YC data is represented as 8-bit data. When YUV format: Luminance: Y: 0 to 1, Chrominance: U: -0.5 to +0.5, V: -0.5 to +0.5 RBG: R: 0 to 1, G: 0 to 1, B: 0 to 1 * When YC format: Luminance: Y: 16 to 235 U: 16 to 240 V: 16 to 240 Chrominance: Cb: -112 to 112* Cr: -112 to 112* RBG: R: 16 to 235 G: 16 to 235 B: 16 to 235 Note: * When data is input to the Q2SD video capture input, the value ranges from 16 to 240 because offset of 128 is added. * YCbCr - RGM conversion formula R = Y + (Cr - 128) x 1.37 G = Y - 0.698 x (Cr - 128) - 0.036 x (Cb - 128) B = Y + (Cb - 128) x 1.73 Where Y ranges from 16 to 235, Cr ranges from 16 to 240, and Cb ranges from 16 to 240. YCbCr and RGB Data *
3.6.6
The Q2SD has two circuits which convert YCbCr data into 16-bit RGB data as shown in figure 3.67. Use either of them. When RGB = 1, select VWRY = 0. When RGB = 0, select VWRY = 1.
Rev. 2.0, 09/02, page 127 of 366
RGB = 1 YCbCr/RGB conversion circuit RGB = 0 UGM
VWRY = 1 YCbCr/RGB conversion circuit VWRY = 2
YCbCr data (video capture)
RGB data (display)
Figure 3.67 Conversion of YCbCr Data into RGB Format When the first-stage conversion circuit is selected by setting the RGB bit in VIMR to 1, the YCbCr data sent from the video decoder is converted into RGB data for storage in the UGM. When the second-stage conversion circuit is selected by setting the VWRY bit in DSMR2 to 1, the YCbCr data sent from the video decoder is converted into RGB data when the video screen is displayed. This makes it possible to store data in either the YUV or RGB format. When the first-stage circuit is applied to store RGB data in the UGM, the stored data can provide multi-valued source data for use in drawing. When the foreground or background screen is specified as being in the 16-bit/pixel mode, the RGB video data in a given screen area can be directly captured for display other than on the video screen. When the second-stage conversion circuit is used, the YCbCr data in the video capture area may be captured by the CPU for display elsewhere.
15 R (5 bits) 11 10 G (5 bits) 5 4 B (5 bits) 0
Figure 3.68 The RGB Data Format (16 Bits/Pixel)
3.7
3.7.1
Video Display Function
Video Screen Display
Setting the VWE bit of display mode register 2 (DSMR2) places the data from the video-capture area (VSA0 to 2) indicated by VID of the video-capture mode register (VIMR) on the video screen in 16-bit/pixel mode. When the video-capture function is in operation, the area read for display as the current screen is automatically switched according to the specification in VID. The position at which the video screen is displayed is specified by the video display start position register. Before the VWE bit is set to 1, the initial value should be set to the video display start position register. The display size is specified by the VSIZEX and VSIZEY bits. The data is displayed on an independent window (video screen). Set a display position within the display area specified by DSX/DSY. The size of video screen is the same as that of a captured area. In the non-interlace display mode, the video image can be
Rev. 2.0, 09/02, page 128 of 366
displayed at any desired position. In interlace sync & video and interlace mode, the Y position must be an even number (the lowest available setting is 0). The following conditions apply to the settings in the VPR: Video horizontal-display start-position register (HVPR) * DSX * VSIZEX Video vertical-display start-position register (VVPR) = DSY > VSIZEY
0 DSX
0
Display area
DSY The image must not be drawn beyond the range of the display.
Figure 3.69 Position of the Video Image 3.7.2 Relationship between the Display Mode and Video-Capture Mode
The Q2SD is able to display images in any of three modes according to the setting of the SCM10 bit of the display-mode register (DSMR): the respective modes produce a non-interlace display, interlace display, and interlace sync & video display. Four video-capture modes are available, and the way in which the video data is captured in the UGM varies according to the mode of capture. Select the appropriate display mode for the correct display of the captured video data. (1) Display of Data Captured in Non-Interlace Mode The non-interlace capture mode is used when the video decoder outputs in non-interlace mode. The display of video data is completed for every VC. Capture in this mode is compatible with non-interlace mode. In an interlace sync display, one field is dropped out (missing of field occurs). In interlace sync & video mode, a frame may be composed of even and odd data in reverse order from that in the original frame of video data.
Rev. 2.0, 09/02, page 129 of 366
* Non-interlace capture Video decoder output Video area 0 (V0) Video area 1 (V1) Video area 2 (V2) VID
Frame 1 Frame 2 High or low Frame 1 Frame 2 V0
Frame 3
Frame 4 Frame 4
Frame 5
Frame 6
Frame 7 Frame 7
Frame 8
Frame 5 Frame 3 V1 V2 V0 Frame 6 V1 V2
Frame 8 V0
* Non-interlace mode display Foreground screen (FG) Background screen (BG) Video screen (VW) FB0 BG FB1 Frame 1 FB0 Frame 2 FB1 Frame 3 FB0 Frame 4 FB1 Frame 5 FB0 Frame 6 FB1 Frame 7
* Interlace mode display (when ODEV = 0) Foreground screen (FG) Background screen (BG) Video screen (VW)
FB0 BG
FB0
FB1 Frame 2
FB1
FB0 Frame 4
FB0
FB1 Frame 6
FB1
(when ODEV = 0) Foreground screen (FG) Background screen (BG) Video screen (VW)
FB0 BG Frame 1
FB0
FB1 Frame 3
FB1
FB0 Frame 5
FB0
FB1 Frame 7
* Interlace sync & video mode display (when ODEV = 0) Foreground screen (FG) Background screen (BG) Video screen (VW)
(when ODEV = 0) Foreground screen (FG) Background screen (BG) Video screen (VW)
Figure 3.70 The Display of Data Captured in Interlace Mode and Display (2) Display of Data Captured in Interlace Composite Mode
,,,,,,,,,, ,,,,,,,,,,
FB0 BG FB1 FB0 FB1 FB0 FB1 FB0 FB1 Frame 1 Frame 2 Even 3 Frame 4 Frame 5 Frame 6 Frame 7 FB0 FB1 FB0 FB1 FB0 FB1 FB0 BG Frame 1 Frame 2 Even 3 Frame 4 Frame 5 Frame 6 Frame 7
Interlace composite mode is used when the video decoder outputs in interlace 2 format. In this capture mode, a frame of video data is displayed every 2 VC, and the data is composed at the UGM area. Capture in this mode is compatible with non-interlace and interlace mode. However, in interlace sync & video display mode, a frame may be incorrectly composed (e.g., the ODD data for V0 is combined with the EVEN data of V1) if the start of the capture operation does not match the start of the frame. If synchronization of the display of data with the timing of the data being captured is left to chance, there will be a 50% probability of the incorrect composition of the displayed frames.
Rev. 2.0, 09/02, page 130 of 366
Different Frame composed
* Interlace composite capture Even 1 Video decoder output (VINM = 1) Video area 0 (V0) Even 1 Video area 1 (V1) Video area 2 (V2) VID * Non-interlace mode display Foreground screen (FG) Background screen (BG) Video screen (VW) FB0 BG
Odd 1 Odd 1
Even 2
Odd 2
Even 3
Odd 3
Even 4 Even 4
Odd 4 Odd 4
Even 2 V0
Odd 2 Even 3 V1 Odd 3 V2
FB1
FB0 Frame 1
FB1 Frame 1
FB0 Frame 2
FB1 Frame 2
FB0 Frame 3
FB1 Frame 3
* Interlace mode display (when ODEV = 0) Foreground screen (FG) Background screen (BG) Video screen (VW)
FB0 BG
FB0
FB1 Frame 1
FB1
FB0 Frame 2
FB0
FB1 Frame 3
FB1
(when ODEV = 0) Foreground screen (FG) Background screen (BG) Video screen (VW)
FB0 BG
FB0
FB1 Frame 1
FB1
FB0 Frame 2
FB0
FB1 Frame 3
* Interlace sync & video mode display (when ODEV = 0) Foreground screen (FG) Background screen (BG) Video screen (VW)
FB0 BG
FB1
FB0 Odd 1
FB1 Even 1
FB0 Odd 2
FB1 Even 2
FB0 Odd 3
FB1 Even 3
(when ODEV = 0) Foreground screen (FG) Background screen (BG) Video screen (VW)
Figure 3.71 The Display of Data Captured in the Interlace Composite Mode (3) Display of Data Captured in Interlace Odd-Only Mode
,,,,,,,,,,
FB0 FB1 FB0 FB1 FB0 FB1 FB0 BG Odd 1 Even 1 Odd 2 Even 2 Odd 3 Even 3
Interlace odd-only mode is used when the video decoder output in interlace format. In this capture mode, only the odd-field video data is captured for display. This mode is compatible with the non-interlace and interlace modes. However, in the interlace sync & video display mode, a frame may be incorrectly composed (e.g., the ODD data for V0 is combined with the EVEN data of V1) if the start of the capture operation does not match the start of the frame. If synchronization of the display of data with the timing of the data being captured is left to chance, there will be a 50% probability of the incorrect composition of the displayed frames.
Rev. 2.0, 09/02, page 131 of 366
Different Frame composed
* Interlace odd capture Video decoder output Video area 0 (V0) Video area 1 (V1) Video area 2 (V2) VID
Even 1
Odd 1 Odd 1
Even 2
Odd 2
Even 3
Odd 3
Even 4
Odd 4 Odd 4
Odd 2 Odd 3 V0 V1 V2
* Non-interlace mode display Foreground screen (FG) Background screen (BG) Video screen (VW) FB0 BG FB1 FB0 Odd 1 FB1 Odd 1 FB0 Odd 2 FB1 Odd 2 FB0 Odd 3 FB1 Odd 3
* Interlace mode display (when ODEV = 0) Foreground screen (FG) Background screen (BG) Video screen (VW)
FB0 BG
FB0
FB1 Odd 1
FB1
FB0 Odd 2
FB0
FB1 Odd 3
FB1
(when ODEV = 0) Foreground screen (FG) Background screen (BG) Video screen (VW)
FB0 BG
FB0
FB1 Odd 1
FB1
FB0 Odd 2
FB0
FB1 Odd 3
* Interlace sync & video mode display (when ODEV = 0) Foreground screen (FG) Background screen (BG) Video screen (VW)
FB0 BG
FB1
FB0 Odd 1
FB1 Odd 1
FB0 Odd 2
FB1 Odd 2
FB0 Odd 3
FB1 Odd 3
(when ODEV = 0) Foreground screen (FG) Background screen (BG) Video screen (VW)
Figure 3.72
,,,,,,,,,,
FB0 FB1 FB0 FB1 FB0 FB1 FB0 BG Odd 1 Odd 1 Odd 2 Odd 2 Odd 3 Odd 3
The Display of Data Captured in the Interlace Odd-Only Mode
(4) Display of Data Captured in Interlace Even-Only Mode Interlace even-only mode is used when the video decoder output in interlace format. In this capture mode, display of video data is completed only by the data of the even field. This mode is compatible with the non-interlace and interlace mode. However, in the interlace sync & video display mode, a frame may be incorrectly composed (e.g., the ODD data for V0 is combined with the EVEN data of V1) if the start of the capture operation does not match the start of the frame. If synchronization of the display of data with the timing of the data being captured is left to chance, there will be a 50% probability of the incorrect composition of the displayed frames.
Rev. 2.0, 09/02, page 132 of 366
Different Frame composed
* Interlace even capture Video decoder output Video area 0 (V0) Video area 1 (V1) Video area 2 (V2) VID Non-interlace mode display Foreground screen (FG) Background screen (BG) Video screen (VW)
Even 1 Even 1
Odd 1
Even 2
Odd 2
Even 3
Odd 3
Even 4 Even 4
Odd 4
Even 2 Even3 V0 V1 V2 V0
FB0 BG
FB1 Even 1
FB0 Even 1
FB1 Even 2
FB0 Even 2
FB1 Even 3
FB0 Even 3
FB1 Even 4
* Interlace mode display (when ODEV = 0) Foreground screen (FG) Background screen (BG) Video screen (VW)
FB0 BG
FB0
FB1 Even 1
FB1
FB0 Even 2
FB0
FB1 Even 3
FB1
(when ODEV = 0) Foreground screen (FG) Background screen (BG) Video screen (VW)
FB0 BG Even 1
FB0
FB1 Even 2
FB1
FB0 Even 3
FB0
FB1 Even 4
* Interlace sync & video mode display (when ODEV = 0) Foreground screen (FG) Background screen (BG) Video screen (VW)
(when ODEV = 0) Foreground screen (FG) Background screen (BG) Video screen (VW)
,,,,,,,,,,
FB0 BG FB1 FB0 FB1 FB0 FB1 FB0 FB1 Even 1 Even 1 Even 2 Even 2 Even 3 Even 3 Even 4 FB0 BG Even 1 Even 1 Even 2 Even 2 Even 3 Even 3 Even 4 FB1 FB0 FB1 FB0 FB1 FB0
Figure 3.73 The Display of Data Captured in the Interlace Even-Only Mode (5) Selecting the Display Mode The result of analysis of compatibility between the video capture mode and Q2SD display mode are given in table 3.13. The entries A in the table indicate combinations that are recommended without reservation. The entries B in the table indicate that a sufficient resolution may be obtained by setting the output of the video decoder to non-interlace mode. However, if this mode is used in interlace mode, the vertical size of the captured image is 1/2 that of the original (i.e., the resolution of the image is halved).
Rev. 2.0, 09/02, page 133 of 366
Different Frame composed
The entries C in the table indicate that the smoothness of the sequence of images will be disrupted (frames will be missing), or different frame composition (blurring or overlap when the shot changes frame to frame) occurs. Table 3.12 Selecting Modes of Video Capture and Display for the Q2SD
Non-interlace Display Mode Noninterlace capture B When the output of the video decoder is set to interlace sync mode, pay attention to the display size (the display size is reduced to 1/2 that of the source size). Interlace Sync Display Mode C Missing frame occurs. When the output of the video decoder is set to interlace sync mode, pay attention to the display size (the display size is reduced to 1/2 that of the source size). A No problem C Interlace Sync & Video Display Mode*2 D Different frames are composed. When the output of the video decoder is set to interlace sync mode, pay attention to the display size (the display size is reduced to 1/2 that of the source size). Different frames are composed.
Interlace composite capture Interlace odd capture
A
No problem (the display is the same as with interlace mode) When the output of the video decoder is set to interlace sync mode, pay attention to the display size (the display size is reduced to 1/2 that of the source 1 size).* When the output of the video decoder is set to interlace sync mode, pay attention to the display size (the display size is reduced to 1/2 that of the source size). 1 *
B
B
When the output of the video decoder is set to interlace sync mode, pay attention to the display size (the display size is reduced to 1/2 that of the source size). 1 * When the output of the video decoder is set to interlace sync mode, pay attention to the display size (the display size is reduced to 1/2 that of the source size). 1 *
C
Different frames are composed. When the output of the video decoder is set to interlace sync mode, pay attention to the display size (the display size is reduced to 1/2 that of the source size).
Interlace even capture
B
B
C
Different frames are composed. When the output of the video decoder is set to interlace sync mode, pay attention to the display size (the display size is reduced to 1/2 that of the source size).
Rev. 2.0, 09/02, page 134 of 366
Notes: 1. When the video decoder is placed in the non-interlace mode, the corresponding mode cannot be used if the FIELD signal is output. 2. The frame is changed field by field (1/60 sec) in Q2SD interlace sync & video display mode since the VID of the video screen is checked for each field. The data which belongs to a single screen when captured is not divided into odd and even fields when displayed. After only a half of captured data has been displayed, the next captured data starts to be displayed. Therefore, the data in the Y direction are halved when the data is captured in interlace, interlace odd-only, or interlace even-only mode in which a frame consists of two-field. If the data captured in this way is displayed on a monitor in non-interlace mode, the screen is halved in the Y direction, and if the data captured is displayed on a TV in interlace mode, the screen on which an even field and an odd field for different frames are composed is displayed. When the video data for one frame is captured over 1/30 s in the interlaced-composite capture mode but the first field to be captured is the second in the pair of fields, the timing of the captured data will be incorrect when it is displayed. This may lead to the composite display of data for different frames. To avoid this, enter the external synchronization mode and the video capture signals (the vertical sync input (VVS), horizontal sync input (VHS), and field (VODD) signals) are input to the EXVSYNC, EXHSYNC, and ODDF pins for synchronization.
Rev. 2.0, 09/02, page 135 of 366
Rev. 2.0, 09/02, page 136 of 366
Section 4 Display List
Table 4.1
Type Four-vertex screen drawing
Command List
Command Name POLYGON4A POLYGON4B POLYGON4C Function Performs any four-vertex drawing at rendering coordinates while referencing a multi-valued (8- or 16-bit/pixel) source. Performs any four-vertex drawing at rendering coordinates while referencing a binary (1-bit/pixel) source. Performs any four-vertex drawing at rendering coordinates with a monochrome specification. Draws a solid line 1 to 5 bits in width at rendering coordinates. Draws a solid line 1 to 5 bits in width at rendering coordinates. Draws a polygonal line at rendering coordinates while referencing a binary source. Draws a polygonal line at rendering coordinates while referencing a binary source. Draws a polygon at work coordinates. Draws a polygon at work coordinates. Zeroizes the work coordinates. Draws a 1-bit-wide solid line at work coordinates. Draws a 1-bit-wide solid line at work coordinates. Sets the current pointer. Sets the current pointer. Sets the local offset. Sets the local offset. Sets the system clipping area. Sets the user clipping area. Sets a value in a specific address-mapped register. Changes the display list fetch destination. Makes a subroutine call for the display list. Returns from a subroutine call made by the GOSUB command. Executes no operation. Performs synchronization with the frame change timing. Informs the Q2SD of the end of the display list.
Line drawing
LINE RLINE PLINE RPLINE
Work screen drawing command
FTRAP RFTRAP CLRW
Work line drawing
LINEW RLINEW
Register setting commands
MOVE RMOVE LCOFS RLCOFS SCLIP UCLIP WPR
Sequence control commands
JUMP GOSUB RET NOP3 VBKEM TRAP
Rev. 2.0, 09/02, page 137 of 366
4.1
4.1.1 Function
Four-Vertex Screen Drawing
POLYGON4A
Performs any four-vertex drawing at rendering coordinates while referencing a multi-valued (8or 16-bit/pixel) source. Command Format LNi = 0
15 CODE DRAW MODE TXS TYS TDX TDY
Sign extension Sign extension Sign extension Sign extension Sign extension Sign extension Sign extension Sign extension
Sign Sign Sign Sign Sign Sign Sign Sign
0
DX1 DY1 DX2 DY2 DX3 DY3 DX4 DY4
Rev. 2.0, 09/02, page 138 of 366
LNi = 1, REL = 0
15 CODE DRAW MODE ABSOLUTE SOURCE ADDRESS H ABSOLUTE SOURCE ADDRESS L TDX TDY
Sign extension Sign extension Sign extension Sign extension Sign extension Sign extension Sign extension Sign extension
Sign Sign Sign Sign Sign Sign Sign Sign
0
DX1 DY1 DX2 DY2 DX3 DY3 DX4 DY4
LNi = 1, REL = 1
15 CODE
Sign extension
Sign
0 DRAW MODE RELATIVE SOURCE ADDRESS H
RELATIVE SOURCE ADDRESS L TDX TDY
Sign extension Sign extension Sign extension Sign extension Sign extension Sign extension Sign extension Sign extension
Sign Sign Sign Sign Sign Sign Sign Sign
DX1 DY1 DX2 DY2 DX3 DY3 DX4 DY4
Rev. 2.0, 09/02, page 139 of 366
1. Code B'00000 2. Rendering Attributes
Reference Data Multi-Valued Source O Binary Source Binary Work A DRAW MODE
Reserved
Drawing Destination Specified Color Rendering O Work
TRNS *
STYL *
CLIP O
REL Z
NET *
EOS *
FST O
LNi *
COOF WORK O *
Fixed at 0 O: V: A: *: Z: Blank:
Can be used Can be used (specified color is binary EOS bit value) Referenced depending on mode (valid when WORK = 1) Referenced depending on mode (clear to 0 when FST = 1) Referenced depending on mode (clear to 0 when LNi = 1) Cannot be used (clear to 0)
3. Command Parameters TXS, TYS: Source starting point ABSOLUTE/RELATIVE SOURCE ADDRESS H: Source start upper address (byte address) ABSOLUTE/RELATIVE SOURCE ADDRESS L: Source start lower address (byte address) TDX, TDY: Source size DXn, DYn (n = 1 to 4): Absolute values, rendering coordinates, negative numbers expressed as two's complement
Rev. 2.0, 09/02, page 140 of 366
Description Transfers multi-valued (8- or 16-bit/pixel) source data to any quadrilateral rendering coordinates. The source is always scanned horizontally, but diagonal scanning may be used in the drawing, depending on the shape. In diagonally-scanned drawing, double-writing occurs to fill in gaps. When LNi = 1, set a multiple of 8 pixels as the TDX value. When LNi = 0, set 8 pixels or more as the TDX value. If the TDX setting is less than 8 pixels, multi-valued source references will not be performed normally. 1. When repeated source referencing is selected as a rendering attribute (STYL = 1), the source is not enlarged or reduced, but is referenced repeatedly. 2. When work referencing is selected as a rendering attribute (WORK = 1), only places where the work coordinate pixel is 1 are drawn at rendering coordinates while referencing work coordinates for the same coordinates as the rendering coordinates. 3. When LNi = 0, make TXS and TYS settings in pixel units. 4. When LNi = 1, the linear address space in the UGM can be used for multi-valued source coordinates. See section 3.3.3 (4) multi-valued source coordinates. When LNi = 1, set the upper bits of the source address in SOURCE ADDRESS H, and the lower bits in SOURCE ADDRESS L. When REL = 0, the source address can be specified as an absolute address. When REL = 1, the source address can be specified as a relative address with respect to the UGM address at which the POLYGON4A command code is located. Absolute addresses and relative addresses must be even numbers. If a relative address is negative, its two's complement should be used. In 16-bit/pixel drawing, if the rendering attribute COOF bit is set to 1, the result of adding the value in the COLOR register to the value of the multi-valued source data is drawn. The operation is performed by saturation processing. In 8-bit/pixel drawing, the COOF bit must be cleared to 0. Note on FST Mode When the register attribute FST bit is set to 1, processing is carried out in 4-pixel units. However, operation will be executed normally only if all the following conditions are satisfied; in other cases, operation cannot be guaranteed. Evaluation of these conditions is not performed internally. * Make settings so that the source and destination are rectangles of the same size, with DX1 = DX4 = 4j - 4, DX2 = DX3 = 4k - 1, DY1 = DY2, DY3 = DY4, DX2 - DX1 = 32n - 1 (where j, k, and n are natural numbers). * When FST = 1, no other rendering attributes except CLIP can be used.
Rev. 2.0, 09/02, page 141 of 366
* When this command is used with FST = 1, first use the MOVE, RMOVE, LCOFS, or RLCOFS command to change the clipping range and local offset values to the values given in the descriptions of the individual commands. * Set a multiple of 4 for TXS and TYS. * Operation is valid in 8-bit/pixel and 16-bit/pixel modes. * The local offset values set by the LCOFS and RLCOFS commands must be non-negative. Example
(TXS, TYS) TDY TDX No work specification (WORK = 0) (DX4, DY4) Multi-valued source coordinates Work specification provided (WORK = 1) (DX3, DY3)
(DX1, DY1) (DX2, DY2)
Rendering coordinates
(DX1, DY1) (DX2, DY2)
(DX1, DY1) (DX2, DY2)
(DX4, DY4)
(DX3, DY3) Work coordinates
(DX4, DY4)
(DX3, DY3)
Rendering coordinates
Rev. 2.0, 09/02, page 142 of 366
4.1.2 Function
POLYGON4B
Performs any four-vertex drawing at rendering coordinates while referencing a binary (1-bit/pixel) source. Command Format REL = 0
15 CODE DRAW MODE ABSOLUTE SOURCE ADDRESS H ABSOLUTE SOURCE ADDRESS L TDX TDY
Sign extension Sign extension Sign extension Sign extension Sign extension Sign extension Sign extension Sign extension
Sign Sign Sign Sign Sign Sign Sign Sign
0
DX1 DY1 DX2 DY2 DX3 DY3 DX4 DY4 COLOR 0 COLOR 1
: Fixed at 0
Rev. 2.0, 09/02, page 143 of 366
REL = 1
15 CODE
Sign extension
Sign
0 DRAW MODE RELATIVE SOURCE ADDRESS H
RELATIVE SOURCE ADDRESS L TDX TDY
Sign extension Sign extension Sign extension Sign extension Sign extension Sign extension Sign extension Sign extension
Sign Sign Sign Sign Sign Sign Sign Sign
DX1 DY1 DX2 DY2 DX3 DY3 DX4 DY4 COLOR 0 COLOR 1
: Fixed at 0
Rev. 2.0, 09/02, page 144 of 366
1. Code B'00001 2. Rendering Attributes
Reference Data Multi-Valued Source Binary Source O Binary Work A DRAW MODE
Reserved
Drawing Destination Specified Color Rendering O Work
TRNS O
STYL O*
CLIP O
REL O
NET O
EOS O
Reserved Reserved
HALF O*
WORK O
Fixed at 0 O: V: A: *: Z: Blank:
Fixed at 0
Fixed at 0
Can be used Can be used (specified color is binary EOS bit value) Referenced depending on mode (valid when WORK = 1) Referenced depending on mode (clear to 0 when FST = 1) Referenced depending on mode (clear to 0 when LNi = 1) Cannot be used (clear to 0)
Note: * The STYL bit and HALF bit cannot both be set to 1 at the same time.
3. Command Parameters ABSOLUTE/RELATIVE SOURCE ADDRESS H: 1-bit/pixel source start upper address (byte address) ABSOLUTE/RELATIVE SOURCE ADDRESS L: 1-bit/pixel source start lower address (byte address) TDX, TDY: Source size DXn, DYn (n = 1 to 4): Absolute values, rendering coordinates, negative numbers expressed as two's complement COLOR0, COLOR1: 8- or 16-bit/pixel color specifications
Rev. 2.0, 09/02, page 145 of 366
Description Draws binary (1-bit/pixel) source data in any quadrilateral rendering area, using the colors specified by parameters COLOR0 and COLOR1. For the COLOR0 and COLOR1 data formats, see section 3.2.9, Input Color Data Configuration. The source is always scanned horizontally, but diagonal scanning may be used in the drawing, depending on the shape. In diagonallyscanned drawing, double-writing occurs to fill in gaps. A multiple of 8 pixels must be set as the TDX value. 1. When repeated source referencing is selected as a rendering attribute (STYL = 1), the source is not enlarged or reduced, but is referenced repeatedly. 2. When work referencing is selected as a rendering attribute (WORK = 1), only places where the work coordinate pixel is 1 are drawn at rendering coordinates while referencing work coordinates for the same coordinates as the rendering coordinates. Binary source data is located in an area in the UGM. When REL = 0, the source address can be specified as an absolute address. When REL = 1, the source address can be specified as a relative address with respect to the UGM address at which the POLYGON4B command code is located. Absolute addresses and relative addresses must be even numbers. If a relative address is negative, its two's complement should be used. Example
SOURCE ADDRESS TDY Non-transparent mode (TRNS = 0) (DX4, DY4) (DX3, DY3) Rendering coordinates Transparent mode (TRNS = 1) (DX1, DY1) COLOR 1 Binary source 0 data is transparent. (DX4, DY4) (DX2, DY2)
TDX
COLOR 0 COLOR 1
(DX1, DY1) (DX2, DY2)
Binary source coordinates
(DX3, DY3) Rendering coordinates
Rev. 2.0, 09/02, page 146 of 366
4.1.3 Function
POLYGON4C
Performs any four-vertex drawing at rendering coordinates with a monochrome specification. Command Format
15 CODE
Sign extension Sign extension Sign extension Sign extension Sign extension Sign extension Sign extension Sign extension
Sign Sign Sign Sign Sign Sign Sign Sign
0 DRAW MODE DX1 DY1 DX2 DY2 DX3 DY3 DX4 DY4 COLOR
Rev. 2.0, 09/02, page 147 of 366
1. Code B'00010 2. Rendering Attributes
Reference Data Multi-Valued Source Binary Source Binary Work A DRAW MODE Reserved Fixed at 0 O: V: A: *: Z: Blank: Fixed at 0 Fixed at 0 CLIP O
Reserved
Drawing Destination Specified Color O Rendering O Work
NET *
EOS *
FST O
Reserved Fixed at 0 Fixed at 0
WORK *
Fixed at 0
Can be used Can be used (specified color is binary EOS bit value) Referenced depending on mode (valid when WORK = 1) Referenced depending on mode (clear to 0 when FST = 1) Referenced depending on mode (clear to 0 when LNi = 1) Cannot be used (clear to 0)
3. Command Parameters DXn, DYn (n = 1 to 4): Absolute values, rendering coordinates, negative numbers expressed as two's complement COLOR: 8- or 16-bit/pixel color specification
Rev. 2.0, 09/02, page 148 of 366
Description Draws any quadrilateral in the rendering area in the single color specified by the COLOR parameter. For the COLOR data format, see section 3.2.9, Input Color Data Format Configuration. When work referencing is selected as a rendering attribute (WORK = 1), only places where the work coordinate pixel is 1 are drawn at rendering coordinates while referencing work coordinates for the same coordinates as the rendering coordinates. When the register attribute FST bit is set to 1, processing is carried out in 4-pixel units. However, operation will be executed normally only if all the following conditions are satisfied; in other cases, operation cannot be guaranteed. Evaluation of these conditions is not performed internally. * Make settings so that the source and destination are rectangles of the same size, with DX1 = DX4 = 4j - 4, DX2 = DX3 = 4k - 1, DY1 = DY2, DY3 = DY4, DX2 - DX1 = 32n - 1 (where j, k, and n are natural numbers). * When FST = 1, no other rendering attributes except CLIP can be used. * When this command is used with FST = 1, first use the MOVE, RMOVE, LCOFS, or RLCOFS command to change the clipping range and local offset values to the values given in the descriptions of the individual commands. * Operation is valid in 8-bit/pixel and 16-bit/pixel modes. In 8-bit/pixel mode, set the same 8bit data for the upper and lower color attribute values. * The local offset values set by the LCOFS and RLCOFS commands must be non-negative.
Rev. 2.0, 09/02, page 149 of 366
Example
No work specification (DX1, DY1) COLOR Specified color (DX4, DY4) (DX3, DY3) Rendering coordinates
(DX2, DY2)
Work specification (DX1, DY1) COLOR (DX1, DY1)
(DX2, DY2)
(DX2, DY2)
Specified color (DX4, DY4) (DX3, DY3) Work coordinates (DX4, DY4) (DX3, DY3) Rendering coordinates
Rev. 2.0, 09/02, page 150 of 366
4.2
4.2.1
Line Drawing
LINE
Function Draws a solid line 1 to 5 bits in width at rendering coordinates. Command Format
15 CODE DRAW MODE LINE COLOR n
Sign extension Sign extension Sign extension Sign extension
Sign Sign Sign Sign
0
DX1 DY1 DX2 DY2 . . .
Sign extension Sign extension
Sign Sign
DXn DYn
1. Code B'01100 2. Rendering Attributes
Reference Data Multi-Valued Source Binary Source Binary Work Specified Color O Drawing Destination Rendering O Work
Rev. 2.0, 09/02, page 151 of 366
DRAW MODE Reserved Fixed at 0 O: V: A: *: Z: Blank: Fixed at 0 Fixed at 0 CLIP O
Reserved
NET O
EOS O
FWUL
W2UL
FWDR W2DR
Fixed at 0
0000 to 1111
Can be used Can be used (specified color is binary EOS bit value) Referenced depending on mode (valid when WORK = 1) Referenced depending on mode (clear to 0 when FST = 1) Referenced depending on mode (clear to 0 when LNi = 1) Cannot be used (clear to 0)
3. Command Parameters LINE COLOR: 8- or 16-bit/pixel color specification n (n = 2 to 65,535): Number of vertices DXn (n = 2 to 65,535): Absolute values, rendering coordinates, negative numbers expressed as two's complement DYn (n = 2 to 65,535): Absolute values, rendering coordinates, negative numbers expressed as two's complement Description Draws a polygonal line at rendering coordinates from vertex 1 (DX1, DY1), through vertex 2 (DX2, DY2), ...., vertex n - 1 (DXn - 1, DYn - 1), to vertex n (DXn, DYn), using the single color specified by parameter LINE COLOR. For the LINE COLOR data format, see section 3.2.9, Input Color Data Configuration. Note: 8-point drawing is used.
Rev. 2.0, 09/02, page 152 of 366
Example
n=3 (0, 0)
(DX2, DY2)
(DX3, DY3) (DX1, DY1)
Rendering coordinates
Rev. 2.0, 09/02, page 153 of 366
4.2.2 Function
RLINE
Draws a solid line 1 to 5 bits in width at rendering coordinates. Command Format
15 CODE DRAW MODE LINE COLOR n
Sign Sign
0
DX1 DX2
Sign Sign
DY1 DY2
. . .
Sign
DXn
Sign
DYn
1. Code B'01101 2. Rendering Attributes
Reference Data Multi-Valued Source Binary Source Binary Work Specified Color O DRAW MODE Reserved Fixed at 0 O: V: A: *: Z: Blank: Fixed at 0 Fixed at 0 CLIP O
Reserved
Drawing Destination Rendering O Work
NET O
EOS O
FWUL
W2UL
FWDR W2DR
Fixed at 0
0000 to 1111
Can be used Can be used (specified color is binary EOS bit value) Referenced depending on mode (valid when WORK = 1) Referenced depending on mode (clear to 0 when FST = 1) Referenced depending on mode (clear to 0 when LNi = 1) Cannot be used (clear to 0)
3. Command Parameters LINE COLOR: 8- or 16-bit/pixel color specification
Rev. 2.0, 09/02, page 154 of 366
n (n = 1 to 65,535): Number of vertices DXn, DYn (n = 1 to 65,535): Relative values, rendering coordinates, negative numbers expressed as two's complement Description Draws, at rendering coordinates, a polygonal line comprising line segments (XC, YC) - (XC + DX1, YC + DY1), (XC + DX1, YC + DY1) - (XC + DX1 + DX2, YC + DY1 + DY2), ..., (XC + ... + DXn - 1, YC + ... + DYn - 1) - (XC + ... + DXn - 1 + DXn, YC + ... + DYn - 1 + DYn) to the coordinates specified by the relative shift (DX, DY) from the current pointer values (XC, YC), using the single color specified by parameter LINE COLOR. For the LINE COLOR data format, see section 3.2.9, Input Color Data Format Configuration. The final coordinate point is stored as the current pointer values (XC, YC). Note: 8-point drawing is used. Example
n=2 (0, 0) (XC + DX1, YC + DY1) DX1 DX2 DY2 DY1 (XC + DX1 + DX2, YC + DY1 + DY2) (XC, YC)
Rendering coordinates
Rev. 2.0, 09/02, page 155 of 366
4.2.3 Function
PLINE
Draws a polygonal line at rendering coordinates while referencing a binary source. Command Format
15 CODE DRAW MODE LINE COLOR 0 LINE COLOR 1 SOURCE ADDRESS H SOURCE ADDRESS L LPPT n
Sign extension Sign extension Sign extension Sign extension
Sign Sign Sign Sign
0
TDX
DX1 DY1 DX2 DY2 . . .
Sign extension Sign extension
Sign Sign
DXn DYn
: Fixed at 0
Rev. 2.0, 09/02, page 156 of 366
1. Code B'01110 2. Rendering Attributes
Reference Data Multi-Valued Source Binary Source O DRAW MODE
Reserved
Drawing Destination Specified Color Rendering O Work
Binary Work
TRNS O
Reserved
CLIP O
Reserved
NET O
EOS O
EDG2 O
Reserved
EDG1 O
Reserved
Fixed at 0 O: V: A: *: Z: Blank:
Fixed at 1
Fixed at 0
Fixed at 0
Fixed at 1
Can be used Can be used (specified color is binary EOS bit value) Referenced depending on mode (valid when WORK = 1) Referenced depending on mode (clear to 0 when FST = 1) Referenced depending on mode (clear to 0 when LNi = 1) Cannot be used (clear to 0)
3. Command Parameters LINE COLOR0: 8- or 16-bit/pixel color specification LINE COLOR1: 8- or 16-bit/pixel color specification SOURCE ADDRESS H: 1-bit/pixel source start upper address (byte address) SOURCE ADDRESS L: 1-bit/pixel source start lower address (byte address) TDX: Source size LPPT: Line pattern pointer n (n = 2 to 65,535): Number of vertices DXn (n = 2 to 65,535): Absolute values, rendering coordinates, negative numbers expressed as two's complement DYn (n = 2 to 65,535): Absolute values, rendering coordinates, negative numbers expressed as two's complement
Rev. 2.0, 09/02, page 157 of 366
Description Draws a polygonal line from vertex 1 (DX1, DY1), through vertex 2 (DX2, DY2), ...., vertex n - 1 (DXn - 1, DYn - 1), to vertex n (DXn, DYn). A multiple of 8 pixels must be set for the TDX value. The reference start position of the binary source data can be adjusted by setting a value between 0 and 7 in the line pattern pointer. For example, if 0 is set, referencing starts at the beginning of the source data, while if 5 is set, referencing starts 5 pixels from the beginning of the source data. When STYL = 1, pattern repetition starts at the pixel after [source start position + TDX + LPPT - 1]. The source start address must be an even number. Note: 4-point drawing is used. Example
n=3 TDX (0, 0) SOURCE ADDRESS 1100 1100 1100 1100 L S B M S B
(DX2, DY2)
(DX1, DY1)
(DX3, DY3) TRNS = 1 and STYL = 1 specified Rendering coordinates
Rev. 2.0, 09/02, page 158 of 366
4.2.4 Function
RPLINE
Draws a polygonal line at rendering coordinates while referencing a binary source. Command Format
15 CODE DRAW MODE LINE COLOR 0 LINE COLOR 1 SOURCE ADDRESS H SOURCE ADDRESS L LPPT n
Sign Sign
0
TDX
DX1 DX2
Sign Sign
DY1 DY2
. . .
Sign
DXn : Fixed at 0
Sign
DYn
Rev. 2.0, 09/02, page 159 of 366
1. Code B'01111 2. Rendering Attributes
Reference Data Multi-Valued Source Binary Source O DRAW MODE
Reserved
Drawing Destination Specified Color Rendering O Work
Binary Work
TRNS O
Reserved
CLIP O
Reserved
NET O
EOS O
EDG2 O
Reserved
EDG1 O
Reserved
Fixed at 0 O: V: A: *: Z: Blank:
Fixed at 1
Fixed at 0
Fixed at 0
Fixed at 1
Can be used Can be used (specified color is binary EOS bit value) Referenced depending on mode (valid when WORK = 1) Referenced depending on mode (clear to 0 when FST = 1) Referenced depending on mode (clear to 0 when LNi = 1) Cannot be used (clear to 0)
3. Command Parameters LINE COLOR0: 8- or 16-bit/pixel color specification LINE COLOR1: 8- or 16-bit/pixel color specification SOURCE ADDRESS H: 1-bit/pixel source start upper address (byte address) SOURCE ADDRESS L: 1-bit/pixel source start lower address (byte address) LPPT: Line pattern pointer TDX: Source size n (n = 1 to 65,535): Number of vertices DXn, DYn (n = 1 to 65,535): Relative values, rendering coordinates, negative numbers expressed as two's complement
Rev. 2.0, 09/02, page 160 of 366
Description Draws a polygonal line comprising line segments (XC, YC) - (XC + DX1, YC + DY1), (XC + DX1, YC + DY1) - (XC + DX1 + DX2, YC + DY1 + DY2), ..., (XC + ... + DXn - 1, YC + ... + DYn - 1) - (XC + ... + DXn -1 + DXn, YC + ... + DYn - 1 + DYn) to the coordinates specified by the relative shift (DX, DY) from the current pointer values (XC, YC). The final coordinate point is stored as the current pointer values (XC, YC). A multiple of 8 pixels must be set for the TDX value. The reference start position of the binary source data can be adjusted by setting a value between 0 and 7 in the line pattern pointer. For example, if 0 is set, referencing starts at the beginning of the source data, while if 5 is set, referencing starts 5 pixels from the beginning of the source data. When STYL = 1, pattern repetition starts at the pixel after [source start position + TDX + LPPT - 1]. The source start address must be an even number. Note: 4-point drawing is used. Example
n=2 (0, 0) (XC + DX1, YC + DY1) DX1 DX2 DY2 (XC + DX1 + DX2, YC + DY1 + DY2) TRNS = 1 and STYL = 1 specified Rendering coordinates SOURCE ADDRESS TDX 1100 1100 1100 1100 L S B M S B
DY1
(XC, YC)
Rev. 2.0, 09/02, page 161 of 366
4.3
4.3.1 Function
Work Screen Drawing Command
FTRAP
Draws a polygon at work coordinates. Command Format
15 CODE n
Sign extension Sign extension Sign extension Sign extension Sign extension
Sign Sign Sign Sign Sign
0 DRAW MODE
DXL DX1 DY1 DX2 DY2 . . .
Sign extension Sign extension
Sign Sign
DXn DYn
1. Code B'01000 2. Rendering Attributes
Reference Data Multi-Valued Source Binary Source Binary Work Specified Color Drawing Destination Rendering Work O
Rev. 2.0, 09/02, page 162 of 366
DRAW MODE Reserved Fixed at 0 O: V: A: B: *: Z: Blank: Fixed at 0 Fixed at 0 CLIP O Reserved Fixed at 0 Fixed at 0 EOS B EDG O Fixed at 0 Reserved Fixed at 0 Fixed at 0
Can be used Can be used (specified color is binary EOS bit value) Referenced depending on mode (valid when WORK = 1) Referenced depending on mode (valid when EDG = 1) Referenced depending on mode (clear to 0 when FST = 1) Referenced depending on mode (clear to 0 when LNi = 1) Cannot be used (clear to 0)
3. Command Parameters n (n = 2 to 65,535): Number of vertices DXL: Left-hand side coordinate DXn (n = 2 to 65,535): Absolute value, work coordinate, negative number expressed as two's complement DYn (n = 2 to 65,535): Absolute value, work coordinate, negative number expressed as two's complement Description Draws a polygon with n-1 vertices at work coordinates. Paints n-1 trapezoids at work coordinates using binary EOR, with X = DXL as the left-hand side, and line segments (DX1, DY1) - (DX2, DY2), (DX2, DY2) - (DX3, DY3), ..., (DXn-1, DYn-1) - (DXn, DYn) as the right-hand sides, and with top and bottom bases parallel to the X-axis. Bottom base drawing is not performed. Set the minimum value of DX1 to DXn as DXL. If the draw mode EDG bit is set to 1, an edge line is drawn after the paint operation. The line drawing data is selected with the EOS bit. When setting the EDG bit to 1, set (DXN, DYN) = (DX1, DY1) to give a closed figure.
Rev. 2.0, 09/02, page 163 of 366
Example
n=5 (0, 0) DXL (DX1, DY1)
(DX2, DY2) (DX4, DY4) (DX3, DY3) Work coordinates
Painting order DXL DXL DXL DXL DXL
Order of Listing FTRAP Parameters
n DXL DX1 Listing order DY1 DX2 DY2 DX3 DY3 DX4 DY4 DX1 DY1 Add the starting point at the end
Rev. 2.0, 09/02, page 164 of 366
4.3.2
RFTRAP
Draws a polygon at work coordinates. Command Format
15 CODE n
Sign extension
Sign Sign Sign
0 DRAW MODE
DXL
Sign Sign
DX1 DX2
DY1 DY2
. . .
Sign
DXn
Sign
DYn
1. Code B'01001 2. Rendering Attributes
Reference Data Multi-Valued Source Binary Source Binary Work Specified Color Drawing Destination Rendering Work O DRAW MODE Reserved Fixed at 0 O: V: A: B: *: Z: Blank: Fixed at 0 Fixed at 0 CLIP O Reserved Fixed at 0 Fixed at 0 EOS B EDG O Fixed at 0 Reserved Fixed at 0 Fixed at 0
Can be used Can be used (specified color is binary EOS bit value) Referenced depending on mode (valid when WORK = 1) Referenced depending on mode (valid when EDG = 1) Referenced depending on mode (clear to 0 when FST = 1) Referenced depending on mode (clear to 0 when LNi = 1) Cannot be used (clear to 0)
3. Command Parameters n (n = 1 to 65,535): Number of vertices
Rev. 2.0, 09/02, page 165 of 366
DXL: Left-hand side coordinate, work coordinate, negative number expressed as two's complement DXn, DYn (n = 1 to 65,535): Relative values, work coordinates, negative numbers expressed as two's complement Description Paints n trapezoids at work coordinates using binary EOR, with X = DXL as the left-hand side, and line segments specified by the relative shift (DX, DY) from the current pointer values (XC, YC) ((XC, YC) - (XC + DX1, YC + DY1), (XC + DX1, YC + DY1) - (XC + DX1 + DX2, YC + DY1 + DY2), ..., (XC + ... + DXn - 1, YC + ... + DYn - 1) - (XC + ... + DXn -1 + DXn, YC + ... + DYn - 1 + DYn)) as the right-hand sides, and with top and bottom bases parallel to the Xaxis. Bottom base drawing is not performed. The final coordinate point is stored as the current pointer values (XC, YC). If the draw mode EDG bit is set to 1, an edge line is drawn after the paint operation. The line drawing data is selected with the EOS bit. When setting the EDG bit to 1, set (DX1 + DX2 + ... + DXn = 0, DY1 + DY2 + ... + DYn = 0) to give a closed figure.
Rev. 2.0, 09/02, page 166 of 366
Example
When n = 3 (0, 0) DXL (XC, YC) DX1 DY1 (XC + DX1 + DX2 + DX3, YC + DY1+ DY2+ DY3) DX3 DX2 (XC + DX1, YC + DY1) DY2
(XC + DX1 + DX2, YC + DY1 + DY2) Work coordinates
Painting order DXL DXL DXL DXL
Rev. 2.0, 09/02, page 167 of 366
4.3.3 Function
CLRW
Zeroizes the work coordinates. Command Format
15 CODE
Sign extension Sign extension Sign extension Sign extension
Sign Sign Sign
0 DRAW MODE XMIN YMIN XMAX YMAX
Sign
1. Code B'10100 2. Rendering Attributes
Reference Data Multi-Valued Source Binary Source Binary Work Specified Color Drawing Destination Rendering Work O DRAW MODE Reserved Fixed at 0 O: V: A: *: Z: Blank: Fixed at 0 Fixed at 0 CLIP O Fixed at 0 Fixed at 0 Fixed at 0 Reserved Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0
Can be used Can be used (specified color is binary EOS bit value) Referenced depending on mode (valid when WORK = 1) Referenced depending on mode (clear to 0 when FST = 1) Referenced depending on mode (clear to 0 when LNi = 1) Cannot be used (clear to 0)
3. Command Parameters XMIN, XMAX: Left and right X coordinate values, work coordinates, negative numbers expressed as two's complement YMIN, YMAX: Upper and lower Y coordinate values, work coordinates, negative numbers expressed as two's complement
Rev. 2.0, 09/02, page 168 of 366
Description Zero-clears the area specified by upper-left coordinates (XMIN, YMIN) and lower-right coordinates (XMAX, YMAX) in the work coordinate system. Example
(0, 0) (XMIN, YMIN)
(XMAX, YMAX)
Work coordinates
Rev. 2.0, 09/02, page 169 of 366
4.4
4.4.1 Function
Work Line Drawing
LINEW
Draws a 1-bit-wide solid line at work coordinates. Command Format
15 CODE DRAW MODE n
Sign extension Sign extension Sign extension Sign extension
Sign Sign Sign Sign
0
DX1 DY1 DX2 DY2 . . .
Sign extension Sign extension
Sign Sign
DXn DYn
1. Code B'01010 2. Rendering Attributes
Reference Data Multi-Valued Source Binary Source Binary Work Specified Color V Drawing Destination Rendering Work O
Rev. 2.0, 09/02, page 170 of 366
DRAW MODE Reserved Fixed at 0 O: V: A: *: Z: Blank: Fixed at 0 Fixed at 0 CLIP O Reserved Fixed at 0 Fixed at 0 EOS O Fixed at 0 Reserved Fixed at 0 Fixed at 0 Fixed at 0
Can be used Can be used (specified color is binary EOS bit value) Referenced depending on mode (valid when WORK = 1) Referenced depending on mode (clear to 0 when FST = 1) Referenced depending on mode (clear to 0 when LNi = 1) Cannot be used (clear to 0)
3. Command Parameters n (n = 2 to 65,535): Number of vertices DXn (n = 2 to 65,535): Absolute value, work coordinate, negative number expressed as two's complement DYn (n = 2 to 65,535): Absolute value, work coordinate, negative number expressed as two's complement Description Performs binary drawing at work coordinates of a polygonal line from vertex 1 (DX1, DY1), through vertex 2 (DX2, DY2), ...., vertex n - 1 (DXn - 1, DYn - 1), to vertex n (DXn, DYn). 0 drawing or 1 drawing is selected with the drawing mode EOS bit. Drawing is performed at work coordinates with 0 when EOS = 0, and at work coordinates with 1 when EOS = 1. (Used for border drawing at work coordinates for a polygonal painted figure.) Note: 8-point drawing is used. Example
Rev. 2.0, 09/02, page 171 of 366
n=3 (0, 0)
(DX2, DY2)
(DX3, DY3) (DX1, DY1)
Work coordinates
Rev. 2.0, 09/02, page 172 of 366
4.4.2 Function
RLINEW
Draws a 1-bit-wide solid line at work coordinates. Command Format
15 CODE DRAW MODE n
Sign Sign
0
DX1 DX2
Sign Sign
DY1 DY2
. . .
Sign
DXn
Sign
DYn
1. Code B'01011 2. Rendering Attributes
Reference Data Multi-Valued Source Binary Source Binary Work Specified Color V DRAW MODE Reserved Fixed at 0 O: V: A: *: Z: Blank: Fixed at 0 Fixed at 0 CLIP O Reserved Fixed at 0 Fixed at 0 EOS O Fixed at 0 Reserved Fixed at 0 Fixed at 0 Fixed at 0 Drawing Destination Rendering Work O
Can be used Can be used (specified color is binary EOS bit value) Referenced depending on mode (valid when WORK = 1) Referenced depending on mode (clear to 0 when FST = 1) Referenced depending on mode (clear to 0 when LNi = 1) Cannot be used (clear to 0)
3. Command Parameters n (n = 1 to 65,535): Number of vertices
Rev. 2.0, 09/02, page 173 of 366
DXn, DYn (n = 1 to 65,535): Relative values, work coordinates, negative numbers expressed as two's complement Description Performs binary drawing at work coordinates of a polygonal line comprising line segments (XC, YC) - (XC + DX1, YC + DY1), (XC + DX1, YC + DY1) - (XC + DX1 + DX2, YC + DY1 + DY2), ..., (XC + ... + DXn - 1, YC + ... + DYn - 1) - (XC + ... + DXn -1 + DXn, YC + ... + DYn - 1 + DYn) to the coordinates specified by the relative shift (DX, DY) from the current pointer values (XC, YC). 0 drawing or 1 drawing is selected with the drawing mode EOS bit. Drawing is performed at work coordinates with 0 when EOS = 0, and at work coordinates with 1 when EOS = 1. The final coordinate point is stored as the current pointer values (XC, YC). (Used for border drawing at work coordinates for a polygonal painted figure.) Note: 8-point drawing is used. Example
n=2 (0, 0) (XC + DX1, YC + DY1) DX1 DX2 DY2 DY1 (XC + DX1 + DX2, YC + DY1 + DY2) (XC, YC)
Work coordinates
Rev. 2.0, 09/02, page 174 of 366
4.5
4.5.1 Function
Register Setting Commands
MOVE
Sets the current pointer. Command Format
15 CODE
Sign extension Sign extension
Sign Sign
0 DRAW MODE XC YC
1. Code B'10000 2. Rendering Attributes
Reference Data Multi-Valued Source Binary Source Binary Work Specified Color Drawing Destination Rendering Work
DRAW MODE Reserved Fixed at 0 O: V: A: *: Z: Blank: Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0
Can be used Can be used (specified color is binary EOS bit value) Referenced depending on mode (valid when WORK = 1) Referenced depending on mode (clear to 0 when FST = 1) Referenced depending on mode (clear to 0 when LNi = 1) Cannot be used (clear to 0)
3. Command Parameters XC: Absolute value, rendering coordinate, work coordinate, negative number expressed as two's complement YC: Absolute value, rendering coordinate, work coordinate, negative number expressed as two's complement
Rev. 2.0, 09/02, page 175 of 366
Description Sets the values obtained by adding the local offset values to XC and YC in the current pointers. XC and YC are set as absolute coordinates. The current pointers are used by relative drawing commands only. After issuing a MOVE command, use relative drawing commands in succession. If an absolute drawing command is used during this sequence, the current pointers will be used as registers for internal computation, and the current pointer values will be lost. A MOVE command must be therefore be issued before using relative drawing commands again. Example
(0, 0)
(XC, YC)
Work coordinates Rendering coordinates
Rev. 2.0, 09/02, page 176 of 366
4.5.2 Function
RMOVE
Sets the current pointer. Command Format
15 CODE
Sign
0 DRAW MODE
Sign
XC
YC
1. Code B'10001 2. Rendering Attributes
Reference Data Multi-Valued Source Binary Source Binary Work Specified Color Drawing Destination Rendering Work
DRAW MODE Reserved Fixed at 0 O: V: A: *: Z: Blank: Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0
Can be used Can be used (specified color is binary EOS bit value) Referenced depending on mode (valid when WORK = 1) Referenced depending on mode (clear to 0 when FST = 1) Referenced depending on mode (clear to 0 when LNi = 1) Cannot be used (clear to 0)
3. Command Parameters XC, YC: Relative values, rendering coordinates, work coordinates, negative numbers expressed as two's complement
Rev. 2.0, 09/02, page 177 of 366
Description Adds XC and YC to the current pointers. Example
(0, 0)
Old (XC, YC) (XC, YC)
(Old XC + XC, Old YC + YC) Rendering coordinates Work coordinates
Rev. 2.0, 09/02, page 178 of 366
4.5.3 Function
LCOFS
Sets the local offset. Command Format
15 CODE
Sign extension Sign extension
Sign Sign
0 DRAW MODE XO YO
1. Code B'10010 2. Rendering Attributes
Reference Data Multi-Valued Source Binary Source Binary Work Specified Color Drawing Destination Rendering Work
DRAW MODE Reserved Fixed at 0 O: V: A: *: Z: Blank: Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0
Can be used Can be used (specified color is binary EOS bit value) Referenced depending on mode (valid when WORK = 1) Referenced depending on mode (clear to 0 when FST = 1) Referenced depending on mode (clear to 0 when LNi = 1) Cannot be used (clear to 0)
3. Command Parameters XO, YO: Local offset value absolute specifications, rendering coordinates, work coordinates, negative numbers expressed as two's complement
Rev. 2.0, 09/02, page 179 of 366
Description Sets the local offset with absolute coordinates. After these settings are made, these offset values are added in all subsequent coordinate specifications. These settings must be made at the start of the display list (the initial values are undefined). To reflect the local offset values in the current pointers, issue a MOVE command after the LCOFS command. When using a command that employs the FST specification, a multiple of 4 must be set for the XO value. Use non-negative values for both XO and YO. Example
(0, 0) (XO1 + DX2, YO1 + DY2)
(XO1, YO1)
LINE
(XO1 + DX1, YO1 + DY1)
Work coordinates Rendering coordinates
Rev. 2.0, 09/02, page 180 of 366
4.5.4 Function
RLCOFS
Sets the local offset. Command Format
15 CODE
Sign
0 DRAW MODE
Sign
XO
YO
1. Code B'10011 2. Rendering Attributes
Reference Data Multi-Valued Source Binary Source Binary Work Specified Color Drawing Destination Rendering Work
DRAW MODE Reserved Fixed at 0 O: V: A: *: Z: Blank: Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0
Can be used Can be used (specified color is binary EOS bit value) Referenced depending on mode (valid when WORK = 1) Referenced depending on mode (clear to 0 when FST = 1) Referenced depending on mode (clear to 0 when LNi = 1) Cannot be used (clear to 0)
3. Command Parameters XO, YO: Local offset value relative specifications, rendering coordinates, work coordinates, negative numbers expressed as two's complement
Rev. 2.0, 09/02, page 181 of 366
Description Adds XO and YO to the local offset. After these settings are made, these offset values are added in all subsequent coordinate specifications. To reflect the local offset values in the current pointers, issue a MOVE command after setting the local offset with the LCOFS or RLCOFS command. When using a command that employs the FST specification, the value obtained by adding XO to the local offset must be a multiple of 4. The local offset values set by XO and YO must be non-negative. Example
(0, 0) (Old XO + XO + DX2, old YO + YO + DY2) XO (Old XO, old YO) YO LINE (Old XO + XO, old YO + YO) (Old XO + XO + DX1, old YO + YO + DY1)
Work coordinates Rendering coordinates
Rev. 2.0, 09/02, page 182 of 366
4.5.5 Function
SCLIP
Sets the system clipping area. Command Format
15 CODE DRAW MODE XMAX YMAX
: Fixed at 0
0
1. Code B'10111 2. Rendering Attributes
Reference Data Multi-Valued Source Binary Source Binary Work Specified Color Drawing Destination Rendering Work
DRAW MODE Reserved Fixed at 0 O: V: A: *: Z: Blank: Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0
Can be used Can be used (specified color is binary EOS bit value) Referenced depending on mode (valid when WORK = 1) Referenced depending on mode (clear to 0 when FST = 1) Referenced depending on mode (clear to 0 when LNi = 1) Cannot be used (clear to 0)
3. Command Parameters XMAX: Left and right X coordinate values, rendering coordinates, work coordinates YMAX: Upper and lower Y coordinate values, rendering coordinates, work coordinates
Rev. 2.0, 09/02, page 183 of 366
Description Designates the area specified by upper-left coordinates (0, 0) and lower-right coordinates (XMAX, YMAX) in the rendering coordinate and work coordinate systems as the system clipping area. The local offset values specified by the LCOFS or RLCOFS command are not added to the coordinates set by this command. Set the maximum drawing range values for XMAX and YMAX. After powering on, the initial values of the clipping range are undefined. The clipping range must therefore be set with the SCLIP command at the start of the first display list executed. For the set values given by this command, screen coordinates must be set as reference coordinates. When using a command that employs the FST specification, set a multiple of 4 - 1 as the XMAX value. Example
(0, 0)
(XMAX, YMAX)
Work coordinates Rendering coordinates
Rev. 2.0, 09/02, page 184 of 366
4.5.6 Function
UCLIP
Sets the user clipping area. Command Format
15 CODE DRAW MODE XMIN YMIN XMAX YMAX
: Fixed at 0
0
1. Code B'10101 2. Rendering Attributes
Reference Data Multi-Valued Source Binary Source Binary Work Specified Color Drawing Destination Rendering Work
DRAW MODE Reserved Fixed at 0 O: V: A: *: Z: Blank: Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0
Can be used Can be used (specified color is binary EOS bit value) Referenced depending on mode (valid when WORK = 1) Referenced depending on mode (clear to 0 when FST = 1) Referenced depending on mode (clear to 0 when LNi = 1) Cannot be used (clear to 0)
3. Command Parameters XMIN, XMAX: Left and right X coordinate values, rendering coordinates, work coordinates
Rev. 2.0, 09/02, page 185 of 366
YMIN, YMAX: Upper and lower Y coordinate values, rendering coordinates, work coordinates Description Designates the area specified by upper-left coordinates (XMIN, YMIN) and lower-right coordinates (XMAX, YMAX) in the rendering coordinate and work coordinate systems as a user clipping area. The local offset values specified by the LCOFS or RLCOFS command are not added to the coordinates set by this command. When making these settings, ensure that XMIN < XMAX and YMIN < YMAX, and that the system clipping area is not exceeded. This setting is valid when CLIP = 1. When using a command that employs the FST specification, set a multiple of 4 as the XMIN value, and a multiple of 4 - 1 as the XMAX value. Example
(0, 0) (XMIN, YMIN)
(XMAX, YMAX) Work coordinates Rendering coordinates
Rev. 2.0, 09/02, page 186 of 366
4.5.7 Function
WPR
Sets a value in a specific address-mapped register. Command Format
15 CODE 15 10 RN DATA
: Fixed at 0
0 DRAW MODE
1. Code B'10110 2. Rendering Attributes
Reference Data Multi-Valued Source Binary Source Binary Work Specified Color Drawing Destination Rendering Work
DRAW MODE Reserved Fixed at 0 O: V: A: *: Z: Blank: Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0
Can be used Can be used (specified color is binary EOS bit value) Referenced depending on mode (valid when WORK = 1) Referenced depending on mode (clear to 0 when FST = 1) Referenced depending on mode (clear to 0 when LNi = 1) Cannot be used (clear to 0)
3. Command Parameters RN: Register number DATA: Data
Rev. 2.0, 09/02, page 187 of 366
Description Writes data to the Q2SD's address-mapped registers. The register number is set in RN, and the write data in DATA. When a write is performed to an address-mapped register with this command, select the location to ensure that the currently executing drawing processing is not adversely affected. Also ensure that there is no conflict with access by the SuperH. This command is intended primarily for performing the operations shown in (a) to (e). (a) (b) (c) (d) Change of display start address or drawing start address (RN = 00A, 00B, 04C) Change of multi-valued source or work start address (RN = 00E, 00F) Change of graphic bit mode (RN = 006) Return address setting when performing resumption processing after drawing suspension (RN = 04A, 04B) (e) Change of drawing color offset value when performing drawing processing (RN = 04D)
The registers that can be written to are limited to those listed below. If a write is performed to another register, subsequent operation cannot be guaranteed.
Register No. 00A: 00B: 00E: 00F: 04C: 006: 04A: 04B: 04D: Register Address H014 H016 H01C H01E H098 H00C H094 H096 H09A Name DSA0 DSA1 SSAR WSAR RSAR REMR RTNH RTNL COLOR
Rev. 2.0, 09/02, page 188 of 366
4.6
4.6.1 Function
Sequence Control Commands
JUMP
Changes the display list fetch destination. Command Format REL = 0
15 CODE DRAW MODE
ABSOLUTE JUMP ADDRESS H ABSOLUTE JUMP ADDRESS L : Fixed at 0
0
REL = 1
15 CODE
Sign extension
Sign
0 DRAW MODE
RELATIVE JUMP ADDRESS H
RELATIVE JUMP ADDRESS L : Fixed at 0
1. Code B'11000 2. Rendering Attributes
Reference Data Multi-Valued Source Binary Source Binary Work Specified Color Drawing Destination Rendering Work
Rev. 2.0, 09/02, page 189 of 366
DRAW MODE Reserved Fixed at 0 O: V: A: *: Z: Blank: Fixed at 0 Fixed at 0 Fixed at 0 REL O Fixed at 0 Fixed at 0 Reserved Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0
Can be used Can be used (specified color is binary EOS bit value) Referenced depending on mode (valid when WORK = 1) Referenced depending on mode (clear to 0 when FST = 1) Referenced depending on mode (clear to 0 when LNi = 1) Cannot be used (clear to 0)
3. Command Parameters ABSOLUTE/RELATIVE JUMP ADDRESS H: Absolute/relative jump destination upper address (byte address) ABSOLUTE/RELATIVE JUMP ADDRESS L: Absolute/relative jump destination lower address (byte address) Description Changes the display list fetch destination to the specified address. When REL = 0, the jump destination address can be specified as an absolute address. When REL = 1, the source address can be specified as a relative address with respect to the UGM address at which the command code is located. Absolute addresses and relative addresses must be even numbers. If a relative address is negative, its two's complement should be used. Example
Display list area Register setting command Drawing command JUMP command . . Drawing command Drawing command Drawing starts
Rev. 2.0, 09/02, page 190 of 366
4.6.2 Function
GOSUB
Makes a subroutine call for the display list. Command Format REL = 0
15 CODE DRAW MODE
ABSOLUTE SUBROUTINE ADDRESS H ABSOLUTE SUBROUTINE ADDRESS L : Fixed at 0
0
REL = 1
15 CODE
Sign extension
Sign
0 DRAW MODE
RELATIVE SUBROUTINE ADDRESS H
RELATIVE SUBROUTINE ADDRESS L : Fixed at 0
1. Code B'11001 2. Rendering Attributes
Reference Data Multi-Valued Source Binary Source Binary Work Specified Color Drawing Destination Rendering Work
Rev. 2.0, 09/02, page 191 of 366
DRAW MODE Reserved Fixed at 0 O: V: A: *: Z: Blank: Fixed at 0 Fixed at 0 Fixed at 0 REL O Fixed at 0 Fixed at 0 Reserved Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0
Can be used Can be used (specified color is binary EOS bit value) Referenced depending on mode (valid when WORK = 1) Referenced depending on mode (clear to 0 when FST = 1) Referenced depending on mode (clear to 0 when LNi = 1) Cannot be used (clear to 0)
3. Command Parameters ABSOLUTE/RELATIVE SUBROUTINE ADDRESS H: Absolute/relative subroutine upper address (byte address) ABSOLUTE/RELATIVE SUBROUTINE ADDRESS L: Absolute/relative subroutine lower address (byte address) Description Changes the display list fetch destination to the specified subroutine address. The fetch address is restored by an RET instruction. As only one level of nesting is permitted, it will not be possible to return if a subroutine call is issued within the subroutine. When REL = 0, the subroutine destination address can be specified as an absolute address. When REL = 1, the address can be specified as a relative address with respect to the UGM address at which the command code is located. Absolute addresses and relative addresses must be even numbers. If a relative address is negative, its two's complement should be used.
Rev. 2.0, 09/02, page 192 of 366
Example
Display list area Register setting command Drawing command GOSUB command Drawing command . . Drawing command Subroutine Drawing command RET command Drawing starts
Rev. 2.0, 09/02, page 193 of 366
4.6.3 Function
RET
Returns from a subroutine call made by the GOSUB command. Command Format
15 CODE DRAW MODE 0
1. Code B'11011 2. Rendering Attributes
Reference Data Multi-Valued Source Binary Source Binary Work Specified Color Drawing Destination Rendering Work
DRAW MODE Reserved Fixed at 0 O: V: A: *: Z: Blank: Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0
Can be used Can be used (specified color is binary EOS bit value) Referenced depending on mode (valid when WORK = 1) Referenced depending on mode (clear to 0 when FST = 1) Referenced depending on mode (clear to 0 when LNi = 1) Cannot be used (clear to 0)
Description Restores the display list fetch destination to the address following the source of the subroutine call.
Rev. 2.0, 09/02, page 194 of 366
4.6.4 Function
NOP3
Executes no operation. Command Format
15 CODE DRAW MODE DUMMY DUMMY 0
1. Code B'11110 2. Rendering Attributes
Reference Data Multi-Valued Source Binary Source Binary Work Specified Color Drawing Destination Rendering Work
DRAW MODE Reserved Fixed at 0 O: V: A: *: Z: Blank: Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0
Can be used Can be used (specified color is binary EOS bit value) Referenced depending on mode (valid when WORK = 1) Referenced depending on mode (clear to 0 when FST = 1) Referenced depending on mode (clear to 0 when LNi = 1) Cannot be used (clear to 0)
Description The NOP3 command does not perform any operation. This command, which consists of three words including the command code, simply fetches the next instruction without executing any processing.
Rev. 2.0, 09/02, page 195 of 366
4.6.5 Function
VBKEM
Performs synchronization with the frame change timing. Command Format
15 CODE DRAW MODE DUMMY DUMMY 0
1. Code B'11010 2. Rendering Attributes
Reference Data Multi-Valued Source Binary Source Binary Work Specified Color Drawing Destination Rendering Work
DRAW MODE Reserved Fixed at 0 O: V: A: *: Z: Blank: Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0
Can be used Can be used (specified color is binary EOS bit value) Referenced depending on mode (valid when WORK = 1) Referenced depending on mode (clear to 0 when FST = 1) Referenced depending on mode (clear to 0 when LNi = 1) Cannot be used (clear to 0)
Description When this command is executed, the drawing operation is kept waiting until the timing for a frame change. As soon as the frame change timing has elapsed, control passes to the next command. The frame change timing is every VBK in non-interlace and interlace & video modes, and every FRM in interlace mode. Do not use this command in auto display charge mode.
Rev. 2.0, 09/02, page 196 of 366
4.6.6 Function
TRAP
Informs the Q2SD of the end of the display list. Command Format
15 CODE DRAW MODE 0
1. Code B'11111 2. Rendering Attributes
Reference Data Multi-Valued Source Binary Source Binary Work Specified Color Drawing Destination Rendering Work
DRAW MODE Reserved Fixed at 0 O: V: A: *: Z: Blank: Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0
Can be used Can be used (specified color is binary EOS bit value) Referenced depending on mode (valid when WORK = 1) Referenced depending on mode (clear to 0 when FST = 1) Referenced depending on mode (clear to 0 when LNi = 1) Cannot be used (clear to 0)
Description Halts the drawing operation and sets TRA to 1 in the status register (SR). If TRE is set to 1 in the interrupt enable register (IER), an interrupt is sent to the SuperH. This command must be placed at the end of the display list.
Rev. 2.0, 09/02, page 197 of 366
Example
Display list area Register setting command Drawing command . . . Drawing command Drawing command Interrupt command Drawing stops Drawing starts
Interrupt source TRA occurs If TRE = 1 at this time, an interrupt is generated externally.
Rev. 2.0, 09/02, page 198 of 366
5.1
Table 5.1
Register Address Abbreviation 15 -- -- SRES DRES DEN TVR TVCL FRCL DMCL CECL VBCL TRCL CSCL TVE FRE DME CEE VBE TRE CSE BRE FRM DMF CER VBK TRA CSF DBF BRK FEMP RBRK DC RS SYSR 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Data
R/W
Register Name
A [10:0]
1
--
--
--
000
R/W
System control
DBM1 DBM0 DMA1 DMA0 DAA1 DAA0 Q3 Q2 Q1 Q0 BRCL MES1 MES0
MAT
002 SR SRCR IER MEMR DSMR FLT WRAP BG MWX DSX DSY DSAR DLSAR DLSAL SSAR SSAL WSAL DMASL DMAWR DSWR DMAWL HDS HDE VDS VDE HSWR HCR VSPR VCR H L H L H L CSTR CSTL CDER CDG CSTH DOOR DOG HC VSP VC DOR DOB CDR CDB HSW WSAR H DMASR L L SSAH WSAH DMASH DSA0 DSA1 DLSAH RSAE REMR IEMR X DSR Y 0 1 H L
R
Status
Registers
004
W
Status register clear
Register Map
0
006
R/W
Interrupt enable
008
R/W
Memory mode
00A
R/W
Display mode
TVM1 TVM0 SCM1 SCM0 REF3 REF2 REF1 REF0 GBM2 GBM1 GBM0
YUV MDTP DTP YUV1 YUV0
00C
R/W
Rendering mode
00E
R/W
Input data conversion mode
010
R/W
Display size
012
R/W
014
R/W
Display start address
016
R/W
018
R/W
Display list start address
01A
R/W
01C
R/W
Multi-valued source area start address
01E
R/W
020
R/W
Work area start address DMA transfer start address
022
R/W
024
R/W
DMA transfer word count
026
Section 5 Registers
028
R/W Display Horizontal display start position R/W window Horizontal display end position
02A
R/W
Vertical display start position
02C
R/W
Vertical display end position
02E
R/W
Horizontal sync pulse width
030
R/W
Horizontal scan cycle
032
R/W
Vertical sync position
034
R/W
036
R/W
Vertical scan cycle Display off output
038
R/W
03A
R/W
Color detection
03C
R/W
03E
R
Command status
Rev. 2.0, 09/02, page 199 of 366
040
R
Table 5.1
Register Address Register Name 15 H ISAR ISAL IDSR IDER X BGSR DMAWR EQWR SPWR DSMR2 VPR Reserved VSAH0 VSAL0 VSAR VSAL1 VSAH2 VSAL2 VSIZER VIMR VID1 CSR VID0 BLINKA BLINKB VSIZEX VSIZEY VSAH1 CDED PRI2 VWRY HDIS ODEV CSY1 CSY0 SPW PRI HVP VVP FBD EQW Y H IDSX IDSY IDE BGSX BGSY L X Y 14 13 12 11 10 9 8 7 6 5 4 3 ISAH Abbreviation Data 2
R/W
CS1 A [10:0]
1
0
042
R/W
044
R/W
Image data transfer start address
046
R/W
Image data size
Registers (cont)
048
R/W
04A
W
Image data entry
Rev. 2.0, 09/02, page 200 of 366
DMAWH CE2 CE1 VWE VSIZ4 VSIZ3 VSIZ2 VSIZ1 VSIZ0 VINM ODEN1 ODEN0 RGB HCS1 VCS1 HCS2 VCS2 CSAR CSARL1 CSARL2 CSARH1 CSARH2 VIE
04C
R/W
04E
R/W
Background start coordinate
050
R/W
DMA transfer word count
052
R/W
Equalizing pulse width
054
R/W
056
R/W
Separation width Display mode 2
058
R/W
Video display start position
05A R/W 0 05C to 060 R/W R/W 062
Video area start address
064 066
R/W
R/W
068
06A
R/W R/W
06C 06E
R/W R/W
Video window size
070
R/W
072
R/W
Video incorporation mode
074
R/W
Cursor display start position
076
078
R/W R/W
07A
R/W
07C
R/W
07E
R/W
Cursor area start address
Table 5.1
Register Address Data 15 X CURR YC LCOR YO UCLR UYMIN UXMAX UYMAX SCLR RTNR RTNL RSAR COLOR 000H CP000R G000 CP001R G001 CP002R G002 000L 001H 001L 002H 002L COOFR Reserved R000 B000 R001 B001 R002 B002 COOFG RSA SXMAX SYMAX RTNH UXMIN XO Y X Y XMIN YMIN XMAX YMAX XMAX YMAX H L XC 14 13 12 11 10 9 8 7 6 5 4 3 Register Name Abbreviation
R/W
CS1 A [10:0]
2
1
0
080
R
Current pointer
082
R
Registers (cont)
084
R
Local offset
086
R
088
R
User clipping area
08A
R
08C
R
08E
R
090
R
System clipping area
092
R
094
R/W
Return address
096
R/W
0
098
R/W
09A
R/W
Rendering start address Color offset
COOFB
09C to 1FE
200
R/W
Color palette
202
R/W
204
R/W
206
R/W
208
R/W
20A
R/W
5EC 255L
R/W
255H
CP255R G255 Reserved
R255 B255
5FE
R/W
Rev. 2.0, 09/02, page 201 of 366
600to 7FE
5.2
Interface Control Registers
The interface control registers are registers related to overall Q2SD control, mapped onto addresses (A10 to A1) H'000 to H'00E, H'056, and H'072. * * * * * * * * * * System control register (SYSR) Status register (SR) Status register clear register (SRCR) Interrupt enable register (IER) Memory mode register (MEMR) Display mode register (DSMR) Display mode 2 register (DSMR2) Rendering mode register (REMR) Input data conversion mode register (IEMR) Video incorporation mode register (VIMR)
Rev. 2.0, 09/02, page 202 of 366
5.2.1
System Control Register (SYSR)
The system control register (SYSR) specifies Q2SD system operation. The SYSR is initialized as follows in a reset: * Bits SRES and DRES are set to 1. * Bits DEN, RBRK, DC, RS, DMA1, DMA0, DAA1, and DAA0 are cleared to 0. * Bits DBM1 and DBM0 retain their values. Register Address: H'000
Bit 15 Bit Name SRES Initial Value 1 R/W R/W Description Software Reset (SRES) Controls execution and suspension of command processing. 0: Command processing execution is enabled. 1: SRES is set to 1 when a hardware reset is performed. Clear to 0 in initialization. When this bit is set to 1 by software, a reset is performed for drawing operations only. In this case, the bit must be set to 1 for at least 16 system operating clock cycles. When SRES is set to 1, the command error flag (CER), trap flag (TRA), command suspend flag (CSF), rendering break bit (RBRK), and drawing break flag (BRK) are cleared to 0.
Rev. 2.0, 09/02, page 203 of 366
Bit 14 13
Bit Name DRES DEN
Initial Value 1 0
R/W R/W R/W
Description Display Reset (DRES) Display Enable (DEN) These bits control starting and stopping of display synchronous operation. 00: Display operation is started. The DRES bit cannot be cleared to 0 while the 5(6(7 pin is low. When using the Q2SD from the initial state, make all control register settings before clearing the DRES bit to 0. When the DEN bit is 0, display data has the value set in the display off output register. 01: Display operation is started. The DRES bit cannot be cleared to 0 while the 5(6(7 pin is low. When using the Q2SD from the initial state, make all control register settings, clear the DRES bit to 0, and then set the DEN bit to 1. Display data has the value stored in the UGM from the next frame. 10: Display synchronous operation is started. The Q2SD only performs UGM refresh operations, regardless of the setting of TVM1 and TVM0 in the display mode register. With these settings, the Q2SD operates as shown below. When switching from DRES, DEN = 01 to DRES, DEN = 10, the setting DRES, DEN = 11 occurs temporarily for reasons relating to internal updating, but this does not affect operation. 1. Drawing is not performed even if the RS bit is set to 1 in SYSR. 2. Display data is all-0 output. 3. The VBK flag is cleared to 0 in SR. 4. Except during video incorporation (VIE = 1), waits are output continuously when UGM access is performed by the CPU or DMA controller. 11: Setting prohibited
12, 11
Reserved Only 0 should be written to these bits.
Rev. 2.0, 09/02, page 204 of 366
Bit 10
Bit Name RBRK
Initial Value 0
R/W R/W
Description Rendering Break (RBRK) Controls rendering (drawing) breaks. This bit should only be set when the BRK bit is cleared to 0. 0: The TRA bit in the status register (SR) is set to 1 by TRAP command execution, and drawing is terminated. 1: The currently executing command ends while the Q2SD is performing drawing, and when the next command is fetched the BRK bit in the status register (SR) is set to 1 and drawing enters the terminated state. The BRK bit does not change if this bit is set to 1 while the Q2SD is not performing drawing. After the break, the start address of the next command is placed in the command status register (CSTR). This bit is cleared to 0 only when a drawing break is effected.
9
DC
0
R/W
Display Area Change (DC) Controls frame buffer switching in manual display change mode. 0: Switching of the frame buffer for display is not performed in manual display change mode. When the DC bit is 0, it can be set to 1. 1: Switching of the frame buffer for display is performed in manual display change mode. This bit can be set to 1 set only when it is 0. Switching is performed in frame units in noninterlace and interlace modes, and in field units in interlace sync & video mode. This bit is cleared to 0 after frame buffer switching, and so should not be cleared to 0 by the SuperH.
Rev. 2.0, 09/02, page 205 of 366
Bit 8
Bit Name RS
Initial Value 0
R/W R/W
Description Rendering Start (RS) Specifies the start of rendering. 0: Rendering is not started. 1: Rendering is started. This bit is cleared to 0 after rendering starts. When this bit is set to 1, all the data held in the FIFO in the CPU interface unit is stored in the UGM. All the data held in the FIFO is also stored in the UGM when the SuperH does not access the UGM for 32 tcyc0 or longer, and when the SuperH reads the UGM.
7 6
DBM1 DBM0
* *
R/W R/W
Double-Buffer Mode 1 and 0 (DBM1, DBM0) These bits select double-buffer control. 00: Auto display change mode is set. 01: Auto rendering mode is set. 10: Manual display change mode is set. 11: Setting prohibited
Rev. 2.0, 09/02, page 206 of 366
Bit 5 4
Bit Name DMA1 DMA0
Initial Value 0 0
R/W R/W R/W
Description DMA Mode (DMA1, DMA0) These bits specify DMA transfer. Use the DMA flag (DMF) in the status register (SR) to check for the beginning and end of DMA mode. 00: Normal mode is set. If DMA transfer is in progress at this time, the transfer data is not guaranteed. 01: The mode for DMA transfer to memory (UGM) corresponding to &6 is set. When the remaining DMA transfer count reaches 0, this bit is automatically cleared and normal mode is entered. The initial value of the remaining DMA transfer count is determined by the setting in the DMA transfer word count register (DMAWR). The remaining DMA transfer count is an internal value in the LSI, and is decremented by 1 each time a word is processed. Do not perform UGM access by the CPU in this mode. If normal mode (DMA1 = 0, DMA0 = 0) is set by the SuperH in this mode, DMA transfer will be aborted. As the value of the transfer data at the time of the abort is undefined, if an abort is performed, DMA transfer must be started over again from the beginning. 10: Setting prohibited 11: The mode for DMA transfer to the register [image data entry register (IDER)] corresponding to &6 is set. In this mode, register address incrementing is not performed and all writes are to IDER. When the remaining DMA transfer count reaches 0, this bit is automatically cleared and normal mode is entered. The initial value of the remaining DMA transfer count is determined by the setting in the DMA transfer word count register (DMAWR). The remaining DMA transfer count is an LSI internal value, and is decremented by 1 each time a word is processed. Do not perform UGM access by the CPU in this mode. If normal mode (DMA1 = 0, DMA0 =0) is set by the SuperH in this mode, DMA transfer will be aborted. As the value of the transfer data at the time of the abort is undefined, if an abort is performed, DMA transfer must be started over again from the beginning. Rev. 2.0, 09/02, page 207 of 366
Bit 3 2
Bit Name DAA1 DAA0
Initial Value 0 0
R/W R/W R/W
Description DMA Address Mode (DAA1, DAA0) Sets the address mode for DMA transfer. 00: Single address mode, data is latched at the rising edge of the 5' signal or the '$&. signal, whichever comes first. 01: Single address mode, with data latched at the rise of the '$&. signal. The 5' signal is ignored. 10: Dual address mode 11: Setting prohibited
1, 0
Reserved The write value should always be 0.
Note: * Value is retained.
Rev. 2.0, 09/02, page 208 of 366
5.2.2
Status Register (SR)
The status register (SR) is used to read the internal status of the Q2SD from outside. The SR is initialized as follows in a reset: * * * * The DBF flag retains its value. The Q flags are set to 0100. The FEMP flag is set to 1. All other flags are cleared to 0.
Register Address: H'002
Bit 15 Bit Name TVR Initial Value 0 R/W R Description TV Sync Signal Error Flag (TVR) Flag that indicates that (;96<1& has been detected within the vertical cycle. 0: The rise of (;96<1& has been detected each time within the vertical cycle determined by the vertical scan cycle register (VCR) setting after the TVR flag has been cleared by the DRES bit in SYSR or the TVCL bit in SRCR. 1: In TV sync mode (bits TVM1 and TVM0 = 10 in DSMR), a rise of (;96<1& has not been detected within the vertical cycle determined by the VCR set value. The TVR flag retains its state until cleared by a reset or by software. 14 FRM 0 R Frame Flag (FRM) Flag that indicates the vertical blanking interval after frame display. 0: Indicates the interval from FRM flag clearing by the DRES bit in SYSR or the FRCL bit in SRCR until the end of the next display in non-interlace mode, or until the end of the next even field display in interlace mode or interlace sync & video mode. 1: Indicates the interval from the first even field vertical blanking interval after FRM flag clearing by the DRES bit in SYSR or the FRCL bit in SRCR until the FRM flag is cleared again (switched in frame units).
Rev. 2.0, 09/02, page 209 of 366
Bit 13
Bit Name DMF
Initial Value 0
R/W R
Description DMA Flag (DMF) Flag that indicates that DMA transfer mode has been initiated and transfer has been completed. 0: DMA transfer mode has not been initiated at all since DMF flag clearing by the DMCL bit in SRCR, or the next DMA transfer mode (bits DMA1 and DMA0 = 01 or 11 in SYSR) has been initiated and the remaining transfer count has not yet reached 0. 1: DMA transfer mode has been initiated and the transfer word count has reached 0. The DMF flag retains its state until cleared by a reset or by software.
12
CER
0
R
Command Error Flag (CER) Flag that indicates that an illegal command has been fetched. 0: Normal state. An illegal command has not been fetched since CER flag clearing by the SRES bit in SYSR or the CECL bit in SRCR. An illegal command is one in which the upper 5 bits of the command code are undefined. The Q2SD does not check the legality of the rendering attributes in the lower 11 bits. 1: Drawing operation halt state. Drawing operation remains halted because an illegal command was fetched after CER flag clearing by the SRES bit in SYSR or the CECL bit in SRCR. The CER flag retains its state until cleared by a reset or by software.
11
VBK
0
R
Vertical Blanking Flag (VBK) Flag that indicates the vertical blanking interval. 0: Indicates the interval from VBK flag clearing by the DRES bit in SYSR or the VBCL bit in SRCR until the end of the next display. 1: Indicates the interval from the first vertical blanking interval after VBK flag clearing by the DRES bit in SYSR or the VBCL bit in SRCR until the VBK flag is cleared again (switched in field units).
Rev. 2.0, 09/02, page 210 of 366
Bit 10
Bit Name TRA
Initial Value 0
R/W R
Description Trap Flag (TRA) Flag that indicates the end of command execution. 0: Indicates the interval from TRA flag clearing by the SRES bit in SYSR or the TRCL bit in SRCR until the end of execution of the next command. 1: Command execution has ended, or the current command is not being executed. The TRA flag retains its state until cleared by a reset or by software.
9
CSF
0
R
Command Suspend Flag (CSF) Flag that indicates that command execution has been suspended due to a frame change in auto display change mode or manual display change mode. 0: Normal operation 1: A rendering end interrupt has not been generated in the interval from CSF flag clearing by the SRES bit in SYSR or the CSCL bit in SRCR until the next frame change. The CSF flag retains its state until cleared by a reset or by software.
8
DBF
*
R
Display Buffer Frame (DBF) Flag that indicates the display start address register used as the display start address by the Q2SD. 0: Address indicated by DSAR0 is being used as display start address. 1: Address indicated by DSAR1 is being used as display start address.
7
BRK
0
R
Drawing Break Flag (BRK) Flag that indicates a drawing break. 0: Indicates the interval until the next drawing break occurs after the BRK flag is cleared by the SRES bit in SYSR or the BRCL bit in SRCR. 1: Indicates that a command is not currently being executed due to a drawing break directive. The BRK flag retains its state until cleared by a reset or by software.
Rev. 2.0, 09/02, page 211 of 366
Bit 6
Bit Name FEMP
Initial Value 1
R/W R
Description FIFO Empty Flag (FEMP) Transfer data from the CPU to the UGM is temporarily stored in a FIFO. These transfers include UGM writes and data transfers via IDR. This flag indicates whether there is UGM storage data in the FIFO. 0: There is UGM storage data in the FIFO. 1: There is no UGM storage data in the FIFO.
5, 4 3 2 1 0
Q3 Q2 Q1 Q0
0 1 0 0
R R R R
Reserved These bits always read 0. Q Flags (Q3 to Q0) Flags used for Q2SD Series product identification. In the Q2SD, these flags read 0100. 0010: HD64411 (Q2) 0011: HD64412 (Q2i) 0100: HD64413A (Q2SD)
Note: * Value is retained.
Rev. 2.0, 09/02, page 212 of 366
5.2.3
Status Register Clear Register (SRCR)
The status register clear register (SRCR) clears the corresponding flags in the status register (SR). Writing 1 to one of bits 15 to 9 or 7 in the SRCR register will clear the corresponding flag in SR to 0. When SR clearing is completed, the value of the SRCR register is cleared to all-0 internally (a read will return 0). Register Address: H'004
Bit 15 14 13 12 11 10 9 8 7 6 to 0 Bit Name TV sync signal error flag clear Frame buffer clear DMA flag clear Command error flag clear Vertical blanking flag clear Trap flag clear Command suspend flag clear Reserved Drawing break flag clear Reserved Abbreviation TVCL FRCL DMCL CECL VBCL TRCL CSCL -- BRCL -- Description Writing 1 to the TCVL bit clears the TVR flag to 0 in SR. Writing 1 to the FRCL bit clears the FRM flag to 0 in SR. Writing 1 to the DMCL bit clears the DMF flag to 0 in SR. Writing 1 to the CECL bit clears the CER flag to 0 in SR. Writing 1 to the VBCL bit clears the VBK flag to 0 in SR. Writing 1 to the TRCL bit clears the TRA flag to 0 in SR. Writing 1 to the CSCL bit clears the CSF flag to 0 in SR. Only 0 should be written to this bit. Writing 1 to the BRCL bit clears the BRK flag to 0 in SR. Only 0 should be written to these bits.
Note: * Value is retained.
Rev. 2.0, 09/02, page 213 of 366
5.2.4
Interrupt Enable Register (IER)
The interrupt enable register (IER) enables or disables interrupts by the corresponding flags in the status register (SR). When a bit in SR is set to 1 and the bit at the corresponding bit position in the IER register is also 1, ,5/ is driven low and an interrupt request is sent to the CPU. The interrupt generation condition is as follows. Interrupt generation condition = ,5/ = DEFGHIJ a = TVRTVE b = FRMFRE c = DMFDME d = CERCEE e = VBKVBE f = TRATRE g = CSFCSE h = BRKBRE Register Address: H'006
Bit 15 Bit Name TVE Initial Value 0 R/W R/W Description TV Sync Signal Error Flag Enable (TVE) Enables or disables interrupts initiated by the TVR flag in SR. 0: Interrupts initiated by the TVR flag in SR are disabled. 1: Interrupts initiated by the TVR flag in SR are enabled. When TVRTVE = 1, an ,5/ interrupt request is sent to the CPU. 14 FRE 0 R/W Frame Flag Enable (FRE) Enables or disables interrupts initiated by the FRM flag in SR. 0: Interrupts initiated by the FRM flag in SR are disabled. 1: Interrupts initiated by the FRM flag in SR are enabled. When FRMFRE = 1, an ,5/ interrupt request is sent to the CPU.
Rev. 2.0, 09/02, page 214 of 366
Bit 13
Bit Name DME
Initial Value 0
R/W R/W
Description DMA Flag Enable (DME) Enables or disables interrupts initiated by the DMF flag in SR. 0: Interrupts initiated by the DMF flag in SR are disabled. 1: Interrupts initiated by the DMF flag in SR are enabled. When DMFDME = 1, an ,5/ interrupt request is sent to the CPU.
12
CEE
0
R/W
Command Error Flag Enable (CEE) Enables or disables interrupts initiated by the CER flag in SR. 0: Interrupts initiated by the CER flag in SR are disabled. 1: Interrupts initiated by the CER flag in SR are enabled. When CERCEE = 1, an ,5/ interrupt request is sent to the CPU.
11
VBE
0
R/W
Vertical Blanking Flag Enable (VBE) Enables or disables interrupts initiated by the VBK flag in SR. 0: Interrupts initiated by the VBK flag in SR are disabled. 1: Interrupts initiated by the VBK flag in SR are enabled. When VBKVBE = 1, an ,5/ interrupt request is sent to the CPU.
10
TRE
0
R/W
Trap Flag Enable (TRE) Enables or disables interrupts initiated by the TRA flag in SR. 0: Interrupts initiated by the TRA flag in SR are disabled. 1: Interrupts initiated by the TRA flag in SR are enabled. When TRATRE = 1, an ,5/ interrupt request is sent to the CPU.
9
CSE
0
R/W
Command Suspend Flag Enable (CSE) Enables or disables interrupts initiated by the CSF flag in SR. 0: Interrupts initiated by the CSF flag in SR are disabled. 1: Interrupts initiated by the CSF flag in SR are enabled. When CSFCSE = 1, an ,5/ interrupt request is sent to the CPU.
Rev. 2.0, 09/02, page 215 of 366
Bit 8 7
Bit Name BRE
Initial Value 0
R/W R/W
Description Reserved Only 0 should be written to this bit. Drawing Break Flag Enable (BRE) Enables or disables interrupts initiated by the BRK flag in SR. 0: Interrupts initiated by the BRK flag in SR are disabled. 1: Interrupts initiated by the BRK flag in SR are enabled. When BRKBRE = 1, an ,5/ interrupt request is sent to the CPU.
6 to 0
Reserved Only 0 should be written to these bits.
5.2.5 Memory Mode Register (MEMR) The memory mode register (MEMR) specifies the size of UGM used and the memory access timing. If the value of this register is modified during a memory access, operation will be temporarily unstable. The MEMR bits MES1, MES0, and MAT are initialized to 0 by a reset. Register Address: H'008
Bit 15 to 6 5 4 Bit Name MES1 MES0 Initial Value 0 0 R/W R/W R/W Description Reserved Only 0 should be written to these bits. Memory Size (MES1, MES0) These bits select the size and quantity of memories used for the UGM. 00: One 16-Mbit (x16) memory, 16-bit bus 01: Two 16-Mbit (x16) memories, 32-bit bus 10: One 64-Mbit (x16) memory, 16-bit bus 11: One 64-Mbit (x32) memory, 32-bit bus
Rev. 2.0, 09/02, page 216 of 366
Bit 3 to 1 0
Bit Name MAT
Initial Value 0
R/W R/W
Description Reserved Only 0 should be written to these bits. Memory Access Timing (MAT) Sets the UGM access timing. APL (Active Precharge Latency) 0: 5 1: 5 Pl (Precharge Latency) 0: 3 1: 2 PCL (RAS-CAS Latency) 0: 3 1: 2 WPL (Write Precharge Latency) 0: 2 1: 2
Rev. 2.0, 09/02, page 217 of 366
5.2.6
Display Mode Register (DSMR)
The display mode register (DSMR) specifies Q2SD display operations. If the value of this register is modified during a display operation, operation will be temporarily unstable. The DSMR is initialized as follows in a reset: Bits WRAP and BG are initialized to 0, bits TVM1 and TVM0 to 10, and bits REF3 to REF0 to 1000. The SCM1 and SCM0 bits retain their values. Register Address: H'005
Bit 15 Bit Name FLT Initial Value 0 R/W R/W Description Filter Mode (FLT) 0: FG and BG pixel data is output for display as the respective screens. 1: FG and BG pixel data is averaged and output for display as the FG screen. Set GBM = 001/101, VWE = 0, PRI = 00, FBD = 0, SCM = 11. FG transparent color determination is not performed. Transparent color determination (CDE) is performed on the result. Set the BG start position one line below the FG start position. The average is found by right-shifting the result of addition of each part in 16-bit format (5:6:5). A fraction of a shift is ignored. 14 to 12 Reserved Only 0 should be written to these bits.
Rev. 2.0, 09/02, page 218 of 366
Bit 11
Bit Name WARP
Initial Value 0
R/W R/W
Description Background Screen Wraparound Mode Configuration (WRAP) 0: Background screen wraparound is not performed. Display contents are not guaranteed if the display area extends beyond the memory installation space. 1: Background screen wraparound is performed. The wraparound units are the number of pixels specified by the MWX bit in the rendering mode register (REMR) in the X direction, and 512 pixels in the Y direction. The start coordinates of this area are indicated by bits 13 to 9 of the background start coordinate register (BGSR).
10
BG
0
R/W
Background Screen Combination (BG) 0: Background screen combination is not performed. 1: Background screen combination is performed.
9, 8
Reserved Only 0 should be written to these bits.
Rev. 2.0, 09/02, page 219 of 366
Bit 7 6
Bit Name TVM1 TVM0
Initial Value 1 0
R/W R/W R/W
Description TV Sync Mode (TVM1, TVM0) These bits specify TV sync mode, in which synchronous operation is performed by means of (;+6<1& and (;96<1& input from an external source, or master mode, in which +6<1& and 96<1& are output. 00: Master mode is set. The Q2SD outputs +6<1&, 96<1&, and 2'') signals. In this mode, when CSY1 = 1 in display mode register 2 (DSMR2), set initial values in the equalizing pulse width register (EQWR) and separation width register (SPWR). 01: Synchronization system switching mode is set. Switching is performed from TV sync mode to master mode, or vice versa, via this mode. In this mode, display operations are forcibly halted and the DISP pin output goes low. The clock supply to the CLK1 pin can also be stopped (input invalidated) (fixed high within the chip). The +6<1&, 96<1&, and 2'') pins are inputs. 10: TV sync mode is set. (;+6<1&, (;96<1&, and 2'') signals are input to the Q2SD. CSYNC output is fixed high. In this mode, clear both CSY1 and CSY0 to 0 in display mode register 2 (DSMR2). 11: Setting prohibited
5 4
SCM1 SCM0
* *
R/W R/W
Scan Mode (SCM1, SCM0) These bits specify the display output scan mode and the unit of display switching. 00: Non-interlace mode: Frame buffer switching can be performed in 1-VC units. 01: Setting prohibited 10: Interlace mode: Frame buffer switching can be performed in 2-VC units. 11: Interlace sync & video mode: Frame buffer switching can be performed in 1-VC units.
Rev. 2.0, 09/02, page 220 of 366
Bit 3 2 1 0
Bit Name REF3 REF2 REF1 REF0
Initial Value 1 0 0 0
R/W R/W R/W R/W R/W
Description Refresh Cycles (REF3 to REF0) These bits specify the number of cycles for which refreshing is performed within one raster in the display screen area. 0000: Refresh timing is not output 0001: Number of refresh cycles = 1 0010: Number of refresh cycles = 2 0011: Number of refresh cycles = 3 0100: Number of refresh cycles = 4 0101: Number of refresh cycles = 5 0110: Number of refresh cycles = 6 0111: Number of refresh cycles = 7 1000: Number of refresh cycles = 8 1001: Number of refresh cycles = 9 1010: Number of refresh cycles = 10 1011: Number of refresh cycles = 11 1100: Number of refresh cycles = 12 1101: Number of refresh cycles = 13 1110: Number of refresh cycles = 14 1111: Number of refresh cycles = 15
Note: * Value is retained.
Rev. 2.0, 09/02, page 221 of 366
5.2.7
Display Mode 2 Register (DSMR2)
The display mode 2 register (DSMR2) specifies Q2SD display operations. If the value of this register is modified during a display operation, operation will be temporarily unstable. In a reset, bits CSY1 and CYS0 retain their values, and the other bits are cleared to 0. Register Address: H'056
Bit 15 to 13 12 Bit Name CDED Initial Value 0 R/W R/W Description Reserved Only 0 should be written to these bits. CDE Disable (CDED) Controls CDE pin output. In TV sync mode (TVM1 = 1, TVM0 = 0), the CDE pin is used to switch between external sync signal generation circuit video output and Q2SD analog R/G/B output. 0: CDE pin output is enabled. 1: CDE pin output is disabled. 11 10 PRI2 VWRY 0 0 R/W R/W Window Priority (PRI2, PRI) These bits set the screen display priority. Video Window RGB/YC Mode (VWRY) Selects whether the data displayed in the video window is stored in the UGM in RGB format or YC format. 0: Video window displays RGB data in the UGM as RGB data. 1: Video window displays YC data in the UGM as RGB data. 9 HDIS 0 R/W [Mode in which Foreground Screen 1 Starts at x = 512 in Case of 1024-Pixel Memory Width] (HDIS) When HDIS = 1, use is possible when GBM = 000 or 001 and RSAE = 0. 0: Foreground screen 1 starts at x = 0. 1: Foreground screen 1 starts at x = 512.
Rev. 2.0, 09/02, page 222 of 366
Bit 8
Bit Name ODEV
Initial Value 0
R/W R/W
Description
2'') Signal Polarity Select (ODEV): Selects the polarity of the 2'') signal.
0: 2'') goes low in first-half field in same frame of interlace display. 1: 2'') goes high in first-half field in same frame of interlace display.
7 6
CSY1 CSY0
* *
R/W R/W
&6<1& Mode (CSY1, CSY0)
These bits select the &6<1& signal output mode in master mode (TVM1 = 0, TVM0 = 0). When CSY1 = 1, values must be set in the equalizing pulse width register (EQWR) and separation width register (SPWR). 00: Waveform determined by exclusive logical OR of 96<1& and +6<1& is output as &6<1&. In TV sync mode (TVM1 = 1, TVM0 = 0), this mode should be selected. 01: Setting prohibited 10: Equalizing pulses are output in 3-raster period from fall of 96<1&, separation in next 3-raster period, equalizing pulses in next 3-raster period, and +6<1& waveform in other periods. 11: Equalizing pulses are output in 2.5-raster period starting 0.5 raster after fall of 96<1&, separation in next 2.5-raster period, equalizing pulses in next 2.5-raster period, and +6<1& waveform in other periods.
5
PRI
0
R/W
Window Priority (PRI2, PRI) These bits set the screen display priority. 00: Screen priority order is: cursor 1, cursor 2, foreground, video, background. 01: Setting prohibited 10: Screen priority order is: cursor 1, foreground, video, cursor 2, background. 11: Screen priority order is: foreground, video, cursor 1, cursor 2, background.
4
Reserved The write value should always be 0.
Rev. 2.0, 09/02, page 223 of 366
Bit 3
Bit Name FBD
Initial Value 0
R/W R/W
Description Foreground Disable (FBD) Selects display or non-display of the foreground screen. 0: Foreground screen is displayed. 1: Foreground screen is not displayed.
2
CE2
0
R/W
Cursor 2 Enable (CE2) Selects display or non-display of cursor 2. 0: Cursor 2 is not displayed. 1: Cursor 2 is displayed. Cursor blinking is always performed. To give the appearance of a nonblinking cursor, make the same setting for cursor blink shapes A and B stored in the cursor area. In Q2SD cursor blinking, cursor blink shapes A and B are displayed alternately. To provide a period in which the cursor is not displayed, make one entire waveform a transparent color.
1
CE1
0
R/W
Cursor 1 Enable (CE1) Selects display or non-display of cursor 1. 0: Cursor 1 is not displayed. 1: Cursor 1 is displayed. Cursor blinking is always performed. To give the appearance of a nonblinking cursor, make the same setting for cursor blink shapes A and B stored in the cursor area. In Q2SD cursor blinking, cursor blink shapes A and B are displayed alternately. To provide a period in which the cursor is not displayed, make one entire waveform a transparent color.
0
VWE
0
R/W
Video Window Enable (VWE) Selects display or non-display of the video window. 0: Video window is not displayed. 1: Video window is displayed. The display contents are not guaranteed if this bit is set before VID changes after VIE is set to 1.
Note: * Value is retained.
Rev. 2.0, 09/02, page 224 of 366
5.2.8
Rendering Mode Register (REMR)
The rendering mode register (REMR) specifies Q2SD rendering operations. If the value of this register is modified during a drawing operation, operation will be temporarily unstable. The exception is modification by a WPR command from the display list, in which case the following conditions must be satisfied: * Changing the MWX setting is prohibited. * For the GBM bits, only the drawing bit configuration can be changed; changing the display bits is prohibited. * RSAE can be changed, on condition that the change agrees with the GBM setting. In a reset, the RSAE bit in the REMR register is cleared to 0, while the MWX and GBM bits retain their values. Register Address: H'00C
Bit 15 Bit Name RSAE Initial Value 0 R/W R/W Description Drawing Start Address Enable (RSAE) Allows the drawing area to be set separately from the display area. The start address of a drawing area separate from the display area is set in the drawing start address register (RSAR). 0: Value in display start address register (DSAR) is used for drawing area. When this setting is made, the GBM setting must be 000 or 001. 1: Value in rendering start address register (RSAR) is used for drawing area. 14 to 7 6 MWX * R/W Reserved Only 0 should be written to these bits. Memory Width (MWX) Specifies the X-direction logical coordinate space of the UGM connected to the Q2SD. 0: X-direction logical coordinate space is 512 pixels 1: X-direction logical coordinate space is 1024 pixels
Rev. 2.0, 09/02, page 225 of 366
Bit 5 to 3 2 1 0
Bit Name GBM2 GBM1 GBM0
Initial Value * * *
R/W R/W R/W R/W
Description Reserved Only 0 should be written to these bits. Graphic Bit Mode 2 to 0 (GBM2 to GBM0) These bits specify the bit configuration of the rendering data and display data handled by the Q2SD. Note that the setting of these bits may be linked to the RSAE bit setting.
Note: * Value is retained.
Table 5.2
Bit Configuration
Description
Bit 2: GBM2 0
Bit 1: GBM1 0 1
Bit 0: GBM0 0 1 0 1 0 1 0 1
FG Bit Configuration 8 bits/pixel 16 bits/pixel 8 bits/pixel 16 bits/pixel 8 bits/pixel 16 bits/pixel 8 bits/pixel 16 bits/pixel
BG Bit Configuration 8 bits/pixel 16 bits/pixel 16 bits/pixel 8 bits/pixel 8 bits/pixel 16 bits/pixel 16 bits/pixel 8 bits/pixel
Rendering Bit Configuration 8 bits/pixel 16 bits/pixel 8 bits/pixel 16 bits/pixel 16 bits/pixel 8 bits/pixel 16 bits/pixel 8 bits/pixel
RSAE Bit Setting 0 or 1 0 or 1 0 or 1 0 or 1 Must be 1 Must be 1 Must be 1 Must be 1
1
0 1
Rev. 2.0, 09/02, page 226 of 366
5.2.9
Input Data Conversion Mode Register (IEMR)
The input data conversion mode register (IEMR) specifies the conversion format for input data from the SuperH. If the value of this register is modified during a data conversion, operation will be temporarily unstable. In a reset, all IEMR bits are cleared to 0. Register Address: H'00E
Bit 15 to 5 4 Bit Name YUV2 Initial Value 0 R/W R/W Description Reserved Only 0 should be written to these bits. YUV Mode: This bit specify whether data input in YUV or YUV format is to be converted to RGB format before being stored in the UGM. 3 MDTP 0 R/W Memory Data Type Mode (MDTP) Specifies whether byte-unit swapping is to be performed in a word access UGM memory write transfer from the SuperH. This bit is valid when bits YUV2 to YUV0 are set to 000, and bits DMA1 and DMA0 are set to either 00 or 01. This bit is invalid for register writes from the SuperH, and also for UGM memory read operations by the SuperH. 0: Byte-unit swapping is not performed in a word access UGM memory write transfer from the SuperH. 1: In a word access UGM memory write transfer from the SuperH, the upper and lower bytes are swapped within the same word (16 bits).
Rev. 2.0, 09/02, page 227 of 366
Bit 2
Bit Name DTP
Initial Value 0
R/W R/W
Description Data Type Mode (DTP) Specifies whether byte-unit swapping is to be performed in a transfer. This bit is valid for data transfers via the image data entry register (IDER). This bit is valid when bits YUV2 to YUV0 are set to 001, 010, 011, or 111, and bits DMA1 and DMA0 are set to either 00 or 11. 0: Byte-unit swapping is not performed in a transfer via IDER. 1: In a transfer via IDER, the upper and lower bytes are swapped within the same word (16 bits).
1 0
YUV1 YUV0
0 0
R/W R/W
YUV Mode: These bits specify whether data input in YUV or YUV format is to be converted to RGB format before being stored in the UGM.
Rev. 2.0, 09/02, page 228 of 366
Table 5.3
Bit 4 YUV2 0 0
YUV Mode Setting
Bit 1 YUV1 0 0 Bit 0 YUV0 0 1 Description Normal mode is set. Data transfer via IDER is not performed. Also used when setting YUV2, 1, 0 to (0, 1, 1). YUV-RGB conversion is performed. When the total number of data conversion pixels reaches 0, these bits are automatically cleared and normal mode is entered. The total number of data conversion pixels is the product of the IDSX and IDSY set values in the image data size register (IDSR). The total number of data conversion pixels is decremented by 1 in the LSI each time a pixel is processed. Do not perform VGM access using the &6 pin in this mode. YUV-RGB conversion is performed. When the total number of data conversion pixels reaches 0, these bits are automatically cleared and normal mode is entered. The total number of data conversion pixels is the product of the IDSX and IDSY set values in the image data size register (IDSR). The total number of data conversion pixels is decremented by 1 in the LSI each time a pixel is processed. Do not perform VGM access using the &6 pin in this mode. 16-bit/pixel data is simply transferred, without conversion. When the total number of data conversion pixels reaches 0, these bits are automatically cleared and normal mode is entered. The total number of data conversion pixels is the product of the IDSX and IDSY set values in the image data size register (IDSR). The total number of data conversion pixels is decremented by 1 in the LSI each time a pixel is processed. Do not perform VGM access using the &6 pin in this mode. Used when setting YUV2, 1, 0 to (1, 1, 1). Setting prohibited Setting prohibited 8-bit/pixel data is simply transferred, without conversion. When the total number of data conversion pixels reaches 0, these bits are automatically cleared and normal mode is entered. The total number of data conversion pixels is the product of the IDSX and IDSY set values in the image data size register (IDSR). Set the number of transfer words (1/2 the number of pixels) as the IDSX value. The total number of data conversion pixels is decremented by 1 in the LSI each time a pixel is processed. Do not perform VGM access using the &6 pin in this mode.
0
1
0
0
1
1
1 1 1 1
0 0 1 1
0 1 0 1
Rev. 2.0, 09/02, page 229 of 366
5.2.10
Video Incorporation Mode Register (VIMR)
The video incorporation mode register (VIMR) is used to make various video capture settings. Register Address: H'072
Bit 15 14 Bit Name VID1 VID0 Initial Value 1 1 R/W R R Description Video Window Status (VID1, VID0) These bits are status flags that indicate the video area storing the most recent image incorporated from the video input. Note that these bits are different in nature from the other bits in this register. The value of these bits is significant only when the VIE bit is cleared to 0. Note that the meaning of these bits is not guaranteed if video capture proceeds while the VIE bit is set to 1. Only 00 should be written to these bits (although the write value is ignored). The meaning of the values read from these bits is shown below. 00: Most recent image is in video area 0. When video window enable (VWE) is 1, video area 0 is displayed. 01: Most recent image is in video area 1. When video window enable (VWE) is 1, video area 1 is displayed. 10: Most recent image is in video area 2. When video window enable (VWE) is 1, video area 2 is displayed. 11: Indicates initial state after a reset. When video window enable (VWE) is 1, video area 0 is displayed. To save or fetch an image as a still picture, video capture must be halted. The sequence of operations is: halt video capture, read the video window status, and fetch the still picture from the relevant area.
Rev. 2.0, 09/02, page 230 of 366
Bit 13 to 10
Bit Name
Initial Value
R/W
Description Reserved Only 0 should be written to these bits (a read will return an undefined value).
9 8 7 6 5 4
VSIZ4 VSIZ3 VSIZ2 VSIZ1 VSIZ0 VINM
0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W
Video Incorporation Reduction (Thinning-Out) Ratio (VSIZ4 to VSIZ0) These bits set the reduction ratio when performing video capture. See table 5.4.
Video Incorporation Mode (VINM) Specifies the field order in video capture. 0: Field for which 92'' input is low (lines 1, 3, 5, ...) is incorporated first, followed by field for which 92'' input is high (lines 2, 4, 6, ...). 1: Field for which 92'' input is high (lines 2, 4, 6, ...) is incorporated first, followed by field for which 92'' input is low (lines 1, 3, 5, ...).
Rev. 2.0, 09/02, page 231 of 366
Bit 3 2
Bit Name ODEN1 ODEN0
Initial Value 0 0
R/W R/W R/W
Description Incorporated Field Select (ODEN1, ODEN0) These bits select the field for which video input scanning method specification and capture are to be performed in video capture. 00: Input video is non-interlace. Do not input interlace signal. 01: Input video is interlace, and frame screens are incorporated with combination of even and odd fields. Supplementing is not performed for operation when fields are combined. 10: Input video is interlace, and only fields for which 92'' signal is low (odd fields) are incorporated. Number of scanning lines of incorporated image is 1/2 number of frame screen scanning lines. 11: Input video is interlace, and only fields for which 92'' signal is high (even fields) are incorporated. Number of scanning lines of incorporated image is 1/2 number of frame screen scanning lines. The vertical size of video storage area (VSIZEY) depends on the setting values of ODEN1 and ODEN0. ODEN1 and ODEN0 are described and the calculation formula of VSIZEY is shown below: * ODEN1 = 0, ODEN0 = 0 The timing of specifying the start address of video storage area is in VVS unit, and data is taken in VVS units. VSIZEY = (number of effective lines existing in 1VVS signals) x (video capture thinning rate) * ODEN1 = 0, ODEN0 = 1 The timing of specifying the start address of video storage area is in 2VVS units, and data of both even and odd-number fields are taken. VSIZEY = (number of effective lines existing in 2VVS signals) x (video capture thinning rate) * ODEN1 = 1 The timing of specifying the start address of video storage area is in 2VVS units, and data of either even or odd-number field is taken. VSIZEY = (number of effective lines existing in 1VVS signals) x (video capture thinning rate)
Rev. 2.0, 09/02, page 232 of 366
Bit 1
Bit Name RGB
Initial Value 0
R/W R/W
Description RGB Conversion Mode (RGB) Selects whether RGB conversion is to be performed in video capture. 0: YUV4:2:2 data is stored directly in UGM, without conversion to RGB. This data cannot be used for any purpose except display in the video window. 1: Data undergoes RGB conversion and is stored in UGM as RGB data. This data can be used as multi-valued source data.
0
VIE
0
R/W
Video Incorporation Enable (VIE) Enables or disables video capture. 0: Video capture is not performed. 1: Video capture is performed.
Table 5.4
Video Incorporation Reduction Ratio
Vertical Reduction Ratio
Bit 9 VSIZ4 0
Bit 8 VSIZ3 0
Bit 7 VSIZ2 0 1
Bit 6 VSIZ1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Horizontal Reduction Ratio VSIZ0 = 0 VSIZ0 = 1 1/2 Setting prohibited Setting prohibited Setting prohibited 1/2 1/6 Setting prohibited Setting prohibited Setting prohibited 1/6 Setting prohibited Setting prohibited Setting prohibited 1/6 Setting prohibited Setting prohibited
1 1 1 1 1/2 1/2 1/2 1/2 1/3 1/3 1/3 1/3 1/4 1/4 1/4 1/4
1 1/3 Setting prohibited Setting prohibited Setting prohibited 1/3 1/4 Setting prohibited Setting prohibited 1/3 Setting prohibited Setting prohibited Setting prohibited Setting prohibited 1/4 Setting prohibited
1
0 1
1
0
0 1
1
0 1
Rev. 2.0, 09/02, page 233 of 366
5.3
Memory Control Registers
The memory control registers are registers related to the unified graphics memory (UGM) configuration, mapped onto addresses (A10 to A1) H'010 to H'01E, H'04C, H'04E, H'062 to H'070, H'07C to H'07E, and H'098. * * * * * * * * * * Display size registers (DSR) Display address registers (DSAR) Display list start address registers (DLSAR) Multi-valued source area start address register (SSAR) Work area start address register (WSAR) Background start coordinate registers (BGSR) Video area start address registers (VSAR) Video window size registers (VSIZER) Cursor area start address register (CSAR) Rendering start address register (RSAR) Display Size Registers (DSR)
5.3.1
The display size registers (DSR) specify the size of the display screen. The number of dots in the horizontal direction is set in DSX, and the number of dots in the vertical direction in DSY. Write 0 to bits that are not used for the DSX and DSY fields (a read will return an undefined value). The DSX and DSY fields in the DSR registers retain their values in a reset. Register Address: H'010
Bit 15 to 10 9 to 0 Bit Name Initial Value * R/W R/W DSX Description
Register Address: H'012
Bit 15 to 9 8 to 0 Bit Name Initial Value * R/W R/W DSY Description
Note: * Value is retained. Rev. 2.0, 09/02, page 234 of 366
5.3.2
Display Address Registers (DSAR)
The display address registers (DSAR) specify the memory areas to be used as UGM frame buffers. Only the upper 7 bits (A22 to A16) of the start physical address of frame buffer 0 (FB0) are set in the DSA0 field in DSAR, and only the upper 7 bits (A22 to A16) of the start physical address of frame buffer 1 (FB1) are set in the DSA1 field in DSAR. The display address register whose contents are actually valid as the display start address is the register indicated by the DBF bit in the status register (SR). The display address register whose contents are not valid as the display start address indicates the rendering coordinate origin when RASE = 0 in the rendering mode register (REMR). When these registers are modified, the new set value becomes valid when an internal update is performed in the case of the display address register whose contents are valid as the display start address, and when an external update (rewrite) is performed in the case of the display address register that indicates the rendering coordinate origin. Write 0 to bits that are not used for the DSA0 and DSA1 fields. The DSA0 and DSA1 fields in the DSAR registers retain their values in a reset. Register Address: H'014
Bit 15 to 7 6 to 0 Bit Name Initial Value * R/W R/W DSA0 (address A22 to A16 setting) Description
Register Address: H'016
Bit 15 to 7 6 to 0 Bit Name Initial Value * R/W R/W DSA1 (address A22 to A16 setting) Description
Note: * Value is retained.
Rev. 2.0, 09/02, page 235 of 366
5.3.3
Display List Start Address Registers (DLSAR)
The display list start address registers (DLSAR) specify the memory area to be used as the display list. The DLSAH and DLSAL fields in DLSAR contain a total of 18 bits, and only the upper bits (A22 to A5) of the start physical address of the display list are set in these fields. Write 0 to bits that are not used for the DLSAH and DLSAL fields (a read will return an undefined value). The DLSAH and DLSA fields in the DLSAR registers retain their values in a reset. Register Address: H'018
Bit 15 to 7 6 to 0 Bit Name Initial Value * R/W R/W DLSAH (address A22 to A16 setting) Description
Register Address: H'01A
Bit 15 to 5 4 to 0 Bit Name Initial Value * R/W R/W Description DLSAL (address A15 to A5 setting)
Note: * Value is retained.
Rev. 2.0, 09/02, page 236 of 366
5.3.4
Multi-Valued Source Area Start Address Register (SSAR)
The multi-valued source area start address register (SSAR) specifies the memory area to be used as the multi-valued source area. The physical address set in this register will be the origin physical address of the multi-valued coordinate. The upper bits (A22 to A16) of the start physical address of the source area are set in the SSAH field, and the lower bits (A15 to A13) in the SSAL field. The settable bit range depends on the highest color representation mode and maximum memory width used in each of the display, drawing, and video areas. In 8-bit/pixel mode with a 512-pixel memory width, all bits can be set. In 8-bit/pixel mode with a 1024-pixel memory width, or 16bit/pixel mode with a 512-pixel memory width, bit 13 should be cleared to 0. In 16-bit/pixel mode with a 1024-pixel memory width, bits 14 and 13 should be cleared to 0. The SSAH and SSAL fields in the SSAR register retain their values in a reset. Register Address: H'01C
Bit 15 to 13 12 to 7 Bit Name Initial Value * R/W R/W Description SSAL (address A15 to A13 setting) Reserved Only 0 should be written to these bits (a read will return an undefined value). 6 to 0 * R/W SSAH (address A22 to A16 setting) Note: * Value is retained.
Rev. 2.0, 09/02, page 237 of 366
5.3.5
Work Area Start Address Register (WSAR)
The work area start address register (WSAR) specifies the memory area to be used as the work area. The physical address set in this register will be the origin physical address of the work coordinate. The upper bits (A22 to A16) of the start physical address of the work area are set in the WSAH field, and the lower bits (A15 to A13) in the WSAL field. The settable bit range depends on the highest color representation mode and maximum memory width used in each of the display, drawing, and video areas. In 8-bit/pixel mode with a 512-pixel memory width, all bits can be set. In 8-bit/pixel mode with a 1024-pixel memory width, or 16bit/pixel mode with a 512-pixel memory width, bit 13 should be cleared to 0. In 16-bit/pixel mode with a 1024-pixel memory width, bits 14 and 13 should be cleared to 0. The WSAH and WSAL fields in the WSAR register retain their values in a reset. Register Address: H'01E
Bit 15 to 13 12 to 7 Bit Name Initial Value * R/W R/W Description WSAL (address A15 to A13 setting) Reserved Only 0 should be written to these bits (a read will return an undefined value). 6 to 0 * R/W WSAH (address A22 to A16 setting) Note: * Value is retained.
Rev. 2.0, 09/02, page 238 of 366
5.3.6
Background Start Coordinate Registers (BGSR)
The background start coordinate registers (BGSR) specify the background start coordinates in the background screen. The settings should be made so that the background screen does not overlap the frame buffers. Write 0 to bits that are not used for the BGSX and BGSY fields (a read will return an undefined value). The BGSX and BGSY bits in the BGSR registers retain their values in a reset. Register Address: H'04C
Bit 15 to 10 9 to 0 Bit Name Initial Value * R/W R/W BGSX Description
Register Address: H'04E
Bit 15, 14 13 to 0 Bit Name Initial Value * R/W R/W BGSY Description
Note: * Value is retained.
Rev. 2.0, 09/02, page 239 of 366
5.3.7
Video Area Start Address Registers (VSAR)
The video area start address registers (VSAR) specify the memory areas used as UGM video areas. Only the upper 13 bits (A22 to A10) of the start physical addresses are specified by the video area start address fields (VSAH, VSAL). Three video storage areas are used, of the size specified by VSIZEX and VSIZEY. Each area has a memory-unit address layout. VSAH0 and VSAL0 are bits that specify the start address of video area 0 (V0). VSAH1 and VSAL1 are bits that specify the start address of video area 1 (V1). VSAH2 and VSAL2 are bits that specify the start address of video area 2 (V2). When the VIE bit in the video incorporation mode register (VIMR) is 1, the area in which the most recent image captured by video capture was stored is automatically selected as the area used for display. When the VIE bit is 0, the video area holding the most recent image is displayed. New values set when these registers are modified become effective when the display is updated internally in the case of display output, or when the next image is incorporated (at the rising edge of the 996 input) in the case of image capture. Write 0 to bits that are not used for VSAH0 to VSAH2 and VSAL0 to VSAL2. (a read will return an undefined value). The VSAR retains the values in a reset. * VSAR0 Register Address: H'062
Bit 15 to 7 6 to 0 Bit Name Initial Value * R/W R/W VSAH0 Description
Register Address: H'064
Bit 15 to 10 9 to 0 Bit Name Initial Value * R/W R/W Description VSAL0
Rev. 2.0, 09/02, page 240 of 366
* VSAR1 Register Address: H'066
Bit 15 to 7 6 to 0 Bit Name Initial Value * R/W R/W VSAH1 Description
Register Address: H'068
Bit 15 to 10 9 to 0 Bit Name Initial Value * R/W R/W Description VSAL1
* VSAR2 Register Address: H'06A
Bit 15 to 7 6 to 0 Bit Name Initial Value * R/W R/W VSAH2 Description
Register Address: H'06C
Bit 15 to 10 9 to 0 Bit Name Initial Value * R/W R/W Description VSAL2
Note: * Value is retained.
Rev. 2.0, 09/02, page 241 of 366
5.3.8
Video Window Size Registers (VSIZER)
The video window size registers (VSIZER) specify the video window display size. Set the value obtained by multiplying the number of effective pixels input from off-chip by the reduction (thinning-out) ratio, VSIZ, at the time of capture. Set 0 for the least significant bits of X and Y as shown in the register diagram. This makes the set values of VSIZEX and VSIZEY even numbers. Write 0 to bits that are not used for the VSIZEX and VSIZEY fields (a read will return an undefined value). The VSIZER retain their values in a reset. Register Address: H'06E
Bit 15 to 10 9 to 1 0 Bit Name Initial Value * R/W R/W VSIZEX Description
Register Address: H'070
Bit 15 to 9 8 to 1 0 Bit Name Initial Value * R/W R/W VSIZEY Description
Note: * Value is retained.
Rev. 2.0, 09/02, page 242 of 366
5.3.9
Cursor Area Start Address Register (CSAR)
The cursor area start address registers (CSAR) specify the memory areas used as cursor areas in the UGM. The upper bits (A22 to A16) of the start physical address of the cursor area are set in the cursor area start address high (CSAH) field, and the lower bits (A15 to A11) in the cursor area start address low (CSAL) field. Set the cursor A shape in the 1024 bytes from the set address, and the cursor B shape in the next 1024 bytes. The new values set when these registers are modified become effective when internal updating is performed. Cursor display data should be set in linear address data format. The CSAL1, CSAL2, CSAH1, and CSAH2 fields in the CSAR registers retain their values in a reset. The cursor 1 area start addresses are set in CSAH1 and CSAL1. The cursor 2 area start addresses are set in CASH2 and CSAL2. * CSAR1 Register Address: H'07C
Bit 15 to 11 10 to 7 Bit Name Initial Value * R/W R/W Description CSAL1 (address A15 to A11 setting) Reserved Only 0 should be written to these bits (a read will return an undefined value). 6 to 0 * R/W CSAH1 (address A22 to A11 setting)
Rev. 2.0, 09/02, page 243 of 366
* CSAR2 Register Address: H'07E
Bit 15 to 11 10 to 7 Bit Name Initial Value * R/W R/W Description CSAL2 (address A15 to A11 setting) Reserved Only 0 should be written to these bits (a read will return an undefined value). 6 to 0 * R/W CSAH2 (address A22 to A16 setting) Note: * Value is retained.
5.3.10
Rendering Start Address Register (RSAR)
The rendering start address register (RSAR) specifies the start address of the rendering area that is valid when the RSAE bit is set to 1 in the rendering mode register (REMR). Only the upper 7 bits (A22 to A16) of the start physical address of the rendering area are set in the RSA field. The RSA field in the RSAR register retains its value in a reset. Register Address: H'098
Bit 15 to 7 Bit Name Initial Value R/W Description Reserved Only 0 should be written to these bits (a read will return an undefined value). 6 to 0 * R/W RSA (address A22 to A16 setting) Note: * Value is retained.
5.4
Display Control Registers
The display control registers are used to set the display timing, and are mapped onto addresses (A10 to A1) H'026 to H'03C, H'052 to H'054, H'058 to H'05A, H'074 to H'07A, and H'200 to H'5FE. * Display window registers (DSWR) * Horizontal sync pulse width register (HSWR) * Horizontal scan cycle register (HCR)
Rev. 2.0, 09/02, page 244 of 366
* * * * * * * * *
Vertical start position register (VSPR) Vertical scan cycle register (VCR) Display off output registers (DOOR) Color detection registers (CDER) Equalizing pulse width register (EQWR) Separation width register (SPWR) Video display start position registers (VPR) Cursor display start position registers (CSR) Color palette registers (CP000R to CP255R) Display Window Registers (DSWR)
5.4.1
The display window registers (DSWR) specify the horizontal and vertical output timing for the display screen. 1. Horizontal Display Start Position (HDS Fields) Field that specifies the horizontal display start position in dot-clock units. 2. Horizontal Display End Position (HDE Fields) Field that specifies the horizontal display end position in dot-clock units. 3. Vertical Display Start Position (VDS Fields) Field that specifies the vertical display start position in raster-line units. 4. Vertical Display End Position (VDE Fields) Field that specifies the vertical display end position in raster-line units. Write 0 to bits that are not used for the HDS, HDE, VDS, and VDE fields (a read will return an undefined value). The HDS, HDE, VDS, and VDE fields in the DSWR registers retain their values in a reset.
Rev. 2.0, 09/02, page 245 of 366
Register Address: H'026
Bit 15 to 9 8 to 0 Bit Name Initial Value * R/W R/W HDS Description
Register Address: H'028
Bit 15 to 10 9 to 0 Bit Name Initial Value * R/W R/W HDE Description
Register Address: H'02A
Bit 15 to 9 8 to 0 Bit Name Initial Value * R/W R/W VDS Description
Register Address: H'02C
Bit 15 to 10 9 to 0 Bit Name Initial Value * R/W R/W VDE Description
Note: * Value is retained.
Rev. 2.0, 09/02, page 246 of 366
5.4.2
Horizontal Sync Pulse Width Register (HSWR)
The horizontal sync pulse width register (HSWR) specifies the horizontal signal low-level pulse width in dot-clock units. The HSW bits in the HSWR register retain their values in a reset. Register Address: H'02E
Bit 15 to 7 Bit Name Initial Value R/W Description Reserved. Only 0 should be written to these bits (a read will return an undefined value). 6 to 0 * R/W HSW Note: * Value is retained.
5.4.3
Horizontal Scan Cycle Register (HCR)
The horizontal scan cycle register (HCR) specifies the horizontal scan cycle in dot-clock units. In TV sync mode (bits TVM1 and TVM0 set to 10 in DSMR), this register setting must be made so that the +6<1& cycle specified by this register is the same as or greater than the (;+6<1& cycle. The HC bits in the HCR register retain their values in a reset. Register Address: H'030
Bit 15 to 11 Bit Name Initial Value R/W Description Reserved. Only 0 should be written to these bits (a read will return an undefined value). 10 to 0 * R/W HC Note: * Value is retained.
5.4.4
Vertical Start Position Register (VSPR)
The vertical start position register (VSPR) specifies the vertical sync signal start position in raster-line units. In TV sync mode (TVM1 = 1, TVM0 = 0 in DSMR), this register setting must be made so that the 96<1& fall setting position specified by this register is the same as or later than the fall of (;96<1&.
Rev. 2.0, 09/02, page 247 of 366
The VSP bits in the VSPR register retain their values in a reset. Register Address: H'032
Bit 15 to 10 Bit Name Initial Value R/W Description Reserved. Only 0 should be written to these bits (a read will return an undefined value). 9 to 0 * R/W VSP Note: * Value is retained.
5.4.5
Vertical Scan Cycle Register (VCR)
The vertical scan cycle register (VCR) specifies the vertical scan interval, including the vertical retrace line interval, in raster-line units. In TV sync mode (TVM1 = 1, TVM0 = 0 in DSMR), set this register so that the 96<1& rise position set with this register is the same as, or later than, the rise of (;96<1&. If a rise of (;96<1& is not detected within the vertical scan interval set in this register, the TVR flag in the status register (SR) will be set to 1. The VC bits in the VCR register retain their values in a reset.
Rev. 2.0, 09/02, page 248 of 366
Register Address: H'034
Bit 15 to 10 Bit Name Initial Value R/W Description Reserved. Only 0 should be written to these bits (a read will return an undefined value). 9 to 0 * R/W VC Note: * Value is retained.
5.4.6
Display Off Output Registers (DOOR)
The display off output registers (DOOR) specify the display data to be output when display is off. A 6-bit setting is made for each of the RGB components, in the DOR fields, DOG fields, and DOB fields. Write 0 to bits that are not used for the DOR, DOG, and DOB fields. The DOR, DOG, and DOB fields in the DOOR registers retain their values in a reset. Register Address: H'036
Bit 15 to 8 7 to 2 1, 0 Bit Name Initial Value * R/W R/W DOR Description
Register Address: H'038
Bit 15 to 10 9, 8 7 to 2 1, 0 Bit Name Initial Value * * R/W R/W R/W DOB Description DOG
Note: * Value is retained.
Rev. 2.0, 09/02, page 249 of 366
5.4.7
Color Detection Registers (CDER)
The color detection registers (CDER) output 1 from the CDE pin, when the output color data (DD17 to DD0) matches the values set in these registers. For details of the output color data format, see section 3.2.11, Q2SD Internal Data Format. The CDR fields in these registers is compared with DD17 to DD12, the CDG field with DD11 to DD6, and the CDB field with DD5 to DD0. As the display data is all-0 outside the display interval, if an all-0 setting is made in CDER, 1 will be output from the CDE pin outside the display interval. Write 0 to bits that are not used for the CDR, CDB, and CDG fields. The CDR, CDG, and CDB fields in the CDER registers retain their values in a reset. Register Address: H'03A
Bit 15 to 8 7 to 2 1, 0 Bit Name Initial Value * R/W R/W CDR Description
Register Address: H'03C
Bit 15 to 10 9, 8 7 to 2 1, 0 Bit Name Initial Value * * R/W R/W R/W CDB Description CDG
Note: * Value is retained.
5.4.8
Equalizing Pulse Width Register (EQWR)
The equalizing pulse width register (EQWR) specifies the low-level pulse width of &6<1& signal equalizing pulses in dot-clock units. Equalizing pulses are generated at the start and in the middle of each raster. This register is valid when CYS1 is set to 1 in display mode 2 register (DSMR2). The EQW bits in the EQWR register retain their values in a reset.
Rev. 2.0, 09/02, page 250 of 366
For example, in the case of the NTSC specification, the low-level pulse width is approximately 2.4 s. If the display operating clock frequency is 14.31818 MHz, a value of 2.4 s x 14.31818 MHz = 35 should be set in this register. Register Address: H'052
Bit 15 to 7 Bit Name Initial Value R/W Description Reserved. Only 0 should be written to these bits (a read will return an undefined value). 6 to 0 * R/W EQW Note: * Value is retained.
5.4.9
Separation Width Register (SPWR)
The separation width register (SPWR) specifies the low-level pulse width of &6<1& signal separation pulses in dot-clock units. Separation pulses are generated at the start and in the middle of each raster. Set an SPW value of less than 1/2 the horizontal scan interval. This register is valid when CYS1 is set to 1 in display mode 2 register (DSMR2). The SPW bits in the SPWR register retain their values in a reset. If HC is the horizontal scan interval, in the case of the NTSC specification, for example, the separation pulse low width is approximately HC/2 - 4.7 s. If HC is 63.555 s and the display operating clock frequency is 14.31818 MHz, a value of (63.555 s/2 - 4.7s) x 14.31818 MHz = 357 should be set in this register.
Rev. 2.0, 09/02, page 251 of 366
Register Address: H'054
Bit 15 to 10 Bit Name Initial Value R/W Description Reserved. Only 0 should be written to these bits (a read will return an undefined value). 9 to 0 * R/W SPW Note: * Value is retained.
5.4.10
Video Display Start Position Registers (VPR)
The video display start position registers (VPR) specify the video horizontal and vertical output timing. 1. Video Horizontal Display Start Position (HVP Fields) This field sets the video horizontal start position in dot-clock units. 2. Video Vertical Display Start Position (VVP Fields) This field sets the video vertical start position in raster-line units. When the SCM1 and SCM0 bits in the display mode register (DSMR) are set to 11 or 10 (interlace sync & video mode or interlace mode), bit 0 in VVP fields should be cleared to 0. Set the start position so that the video display area does not extend beyond the frame buffer display screen. Unlike the HDS and VDS fields in the display window registers (DSWR), the screen coordinate upper-left reference values should be set in the HVP and VVP fields. In the horizontal direction the upper-left point is 0, and the right direction is positive, with changes made one by one in dot units. In the vertical direction the upper-left point is 0, and the downward direction is positive, with changes made one by one in line units. Write 0 to bits that are not used for the HVP and VVP fields (a read will return an undefined value). The HVP and VVP bits in the VPR (HVP/VVP) registers retain their values in a reset. Register Address: H'058
Bit 15 to 10 9 to 0 Bit Name Initial Value * R/W R/W HVP Description
Rev. 2.0, 09/02, page 252 of 366
Register Address: H'05A
Bit 15 to 9 8 to 0 Bit Name Initial Value * R/W R/W VVP Description
Note: * Value is retained.
5.4.11
Cursor Display Start Position Registers (CSR)
The cursor display start position registers (CSR) specify the cursor 1 and 2 horizontal and vertical output timing and the length of the cursor blink shape A and B display intervals. 1. Cursor 1 Horizontal Display Start Position (HCS1) These bits set the cursor 1 horizontal display start position in dot-clock units. 2. Cursor 1 Vertical Display Start Position (VCS1) These bits set the cursor 1 vertical display start position in raster-line units. 3. Cursor 2 Horizontal Display Start Position (HCS2) These bits set the cursor 2 horizontal display start position in dot-clock units. 4. Cursor 2 Vertical Display Start Position (VCS2) These bits set the cursor 2 vertical display start position in raster-line units. 5. Cursor Blink Shape A Display Interval Length (BLNKA) These bits set, in field units, the length of the interval during which cursor shape A (stored in the cursor area) is displayed. These bits should not be cleared to 0. This field is used for both cursor 1 and cursor 2. Display shape switching is performed simultaneously for both cursors. 6. Cursor Blink Shape B Display Interval Length (BLNKB) These bits set, in field units, the length of the interval during which cursor shape B (stored in the cursor area) is displayed. These bits should not be cleared to 0. This field is used for both cursor 1 and cursor 2. Display shape switching is performed simultaneously for both cursors. The cursor is 32 x 32 pixels in size, and is displayed in the color assigned in the color palette register. Set the start positions so that the upper-left coordinates of the cursor display area do not extend outside the frame buffer display screen. Also set the start positions so that cursors 1 and 2 do not overlap, as cursor 1 will have priority and cursor 2 will be lost in this case. Unlike the HDS and VDS fields in the display window registers (DSWR), the screen coordinate upper-left reference values should be set in the HCS and VCS fields. In the horizontal direction the upper-left point is 0, and the right direction is positive, with changes made one by one in dot units. In the vertical direction the upper-left point is 0, and the downward direction is positive, with changes made one by one in line units.
Rev. 2.0, 09/02, page 253 of 366
In cursor blinking, in the cursor display A interval, the 1024 bytes of data from the address specified by the cursor area start address register are used for display. In the cursor display B interval, the 1024 bytes of data from the location obtained by adding 1024 bytes to the address specified by the cursor area start address register are used for display. Write 0 to bits that are not used for the HCS1, VCS1, HCS2, VCS2, BLINKA, and BLINKB fields (a read will return an undefined value). The HCS1, VCS1, HCS2, VCS2, BLINKA, and BLINKB bits in the CSR registers retain their values in a reset. Register Address: H'074
Bit 15 to 10 9 to 0 Bit Name Initial Value * * R/W R/W R/W Description BLNKA HCS1
Register Address: H'076
Bit 15 to 10 9 8 to 0 Bit Name Initial Value * R/W R/W R/W VCS1 Description BLNKB
Register Address: H'078
Bit 15 to 9 8 to 0 Bit Name Initial Value * R/W R/W R/W HCS2 Description
Register Address: H'07A
Bit 15 to 9 8 to 0 Bit Name Initial Value * R/W R/W R/W VCS2 Description
Note: * Value is retained.
Rev. 2.0, 09/02, page 254 of 366
5.4.12
Color Palette Registers (CP000R to CP255R)
The color palette is mapped onto addresses (A10 to A1) H'200 to H'5FE. Settings can be made for 256 colors, with 6 bits each for R, G, and B. The color palette can only be used in 8-bit/pixel mode. When the color palette is accessed by the CPU, bits GBM2 to GBM0 in the rendering mode register (REMR) should be set to 000, 010, 100, or 110. In the Q2SD, the color palette set values are retained regardless of the GBM values. * CP000R Register Address: H'200
Bit 15 to 8 7 to 2 1, 0 Bit Name Initial Value * R/W R/W R000 (Red: 6 bits) Description
Register Address: H'202
Bit 15 to 10 9, 8 7 to 2 1, 0 Bit Name Initial Value * * R/W R/W R/W B000 (Blue: 6 bits) Description G000 (Green: 6 bits)
Rev. 2.0, 09/02, page 255 of 366
* CP001R Register Address: H'204
Bit 15 to 8 7 to 2 1, 0 Bit Name Initial Value * R/W R/W R001 (Red: 6 bits) Description
Register Address: H'206
Bit 15 to 10 9, 8 7 to 2 1, 0 Bit Name Initial Value * * R/W R/W R/W B001 (Blue: 6 bits) Description G001 (Green: 6 bits)
* CP002R : * CP255R Register Address: H'5FC
Bit 15 to 8 7 to 2 1, 0 Bit Name Initial Value * R/W R/W R255 (Red: 6 bits) Description
Register Address: H'5FE
Bit 15 to 10 9, 8 7 to 2 1, 0 Bit Name Initial Value * * R/W R/W R/W B255 (Blue: 6 bits) Description G255 (Green: 6 bits)
Note: * Value is retained.
Rev. 2.0, 09/02, page 256 of 366
5.5
Rendering Control Registers
The rendering control registers are 16-bit registers, mapped onto addresses (A10 to A1) H'03E to H'040, H'080 to H'096, and H'09A. Before the current pointer register (CURR), local offset register (LCOR), user clipping area register (ULCR), system clipping area register (SCLR), or return address register (RTNR) is read, the RBRK of the system control register (SYSR) must be set to 1, and BRK must be 1. When these values are read when BRK is not 1, an invalid value may be read. * * * * * * Command status registers (CSTR) Current pointer registers (CURR) Local offset registers (LCOR) User clipping area registers (UCLR) System clipping area registers (SCLR) Return address registers (RTNR) Command Status Registers (CSTR)
5.5.1
The command status registers (CSTR) store the address of the command word (op code word) being executed when a frame change is performed. The upper bits (A22 to A16) of the command word address are indicated by the CSTH field, and the lower bits (A15 to A1) by the CSTL field. The address indicated by the CSTH and CSTL fields is a word address. Bits that are not used for the CSTH and CSTL fields are always read as 0. The CSTH and CSTL fields in the CSTR registers retain their values in a reset. Register Address: H'03E
Bit 15 to 7 9 to 0 Bit Name Initial Value * R/W R CSTH (address A22 to A16 setting) Description
Rev. 2.0, 09/02, page 257 of 366
Register Address: H'040
Bit 15 to 1 0 Bit Name Initial Value * R/W R Description CSTL (address A15 to A1 setting)
Note: * Value is retained.
5.5.2
Current Pointer Registers (CURR)
The current pointer registers (CURR) indicate the current pointer coordinates. When these registers are read, bits that are not used for the XC and YC fields are always read as 0. The XC and YC bits in the CURR registers retain their values in a reset. Register Address: H'080
Bit 15, 14 13 12 to 0 Bit Name Initial Value * * R/W R R Sign XC Description
Register Address: H'082
Bit 15, 14 13 12 to 0 Bit Name Initial Value * * R/W R R Sign YC Description
Note: * Value is retained.
Rev. 2.0, 09/02, page 258 of 366
5.5.3
Local Offset Registers (LCOR)
The local offset registers (LCOR) indicate the offset coordinates. When these registers are read, bits that are not used for the XO and YO fields are always read as 0. The XO and YO bits in the LCOR registers retain their values in a reset. Register Address: H'084
Bit 15, 14 13 12 to 0 Bit Name Initial Value * * R/W R R Sign XO Description
Register Address: H'086
Bit 15, 14 13 12 to 0 Bit Name Initial Value * * R/W R R Sign YO Description
Note: * Value is retained.
5.5.4
User Clipping Area Registers (UCLR)
The user clipping area registers (UCLR) indicate the user clipping area. When these registers are read, bits that are not used for the UXMIN, UYMIN, UXMAX, and UYMAX fields are always read as 0. The UXMIN, UYMIN, UXMAX, and UYMAX bits in the UCLR registers retain their values in a reset.
Rev. 2.0, 09/02, page 259 of 366
Register Address: H'088
Bit 15, 14 13 12 to 0 Bit Name Initial Value * * R/W R R Sign UXMIN (upper-left X) Description
Register Address: H'08A
Bit 15, 14 13 12 to 0 Bit Name Initial Value * * R/W R R Sign UYMIN (upper-left Y) Description
Register Address: H'08C
Bit 15, 14 13 12 to 0 Bit Name Initial Value * * R/W R R Sign UXMAX (upper-left X) Description
Register Address: H'08E
Bit 15, 14 13 12 to 0 Bit Name Initial Value * * R/W R R Sign UYMAX (upper-left Y) Description
Note: * Value is retained.
Rev. 2.0, 09/02, page 260 of 366
5.5.5
System Clipping Area Registers (SCLR)
The system clipping area registers (SCL) indicate the system clipping area. When these registers are read, bits that are not used for the SXMAX, and SYMAX fields are always read as 0. The SXMAX and SYMAX bits in the SCLR registers retain their values in a reset. Register Address: H'090
Bit 15, 14 13 12 to 0 Bit Name Initial Value * * R/W R R Sign SXMAX (upper-right X) Description
Register Address: H'092
Bit 15, 14 13 12 to 0 Bit Name Initial Value * * R/W R R Sign SYMAX (upper-right Y) Description
Note: * Value is retained.
5.5.6
Return Address Registers (RTNR)
The return address registers (RTNR) specify the return address. The upper bits (A22 to A16) of the start address are set in the RTNH field, and the lower bits (A15 to A1) in the RTNL field. The address (bits A22 to A1) indicated by the RTNH and RTNL fields is a word address. Write 0 to bits that are not used for the RTNH and RTNL fields (a read will return an undefined value). The RTNH and RTNL fields in the RTNR registers retain their values in a reset.
Rev. 2.0, 09/02, page 261 of 366
Register Address: H'094
Bit 15 to 7 6 to 0 Bit Name Initial Value * R/W R/W RTNH (address A22 to A16 setting) Description
Register Address: H'096
Bit 15 to 1 0 Bit Name Initial Value * R/W R Description RTNL (address A15 to A1 setting)
Note: * Value is retained.
5.5.7
Color Offset Register (COLOR)
The offset components are treated as signed integers. This register can be used by the POLYGON4A command. In 16-bit/pixel drawing, if the rendering attribute COOF bit is set to 1, the result of adding the value in the COLOR register to the value of the multi-valued source data is drawn. The operation is performed by saturation processing. In 8-bit/pixel drawing, the rendering attribute COOF bit must be cleared to 0. Register Address: H'09A
Bit 15 14 to 11 10 9 to 5 4 3 to 0 Bit Name Initial Value * * * * * * R/W R/W R/W R/W R/W R/W R/W Description Sign COOFR (Color offset R) Color offset red component Sign COOFG (Color offset G) Color offset green component Sign COOFB (Color offset B) Color offset blue component
Note: * Value is retained.
Rev. 2.0, 09/02, page 262 of 366
5.6
Data Transfer Control Registers
The data transfer control registers are related to the control of input data transfer and conversion, mapped onto addresses (A10 to A1) H'020 to H'024 and H'042 to H'04A. 5.6.1 DMA Transfer Start Address Registers (DMASR)
The DMA transfer start address registers (DMASR) specify the start address of the transfer destination UGM in a DMA transfer. The upper bits (A22 to A16) of the start address are set in the DMASH field in DMASR, and the lower bits (A15 to A1) in the DMASL field in DMASR. If the value of these registers is modified during a series of DMA operations from the time bits DMA1 and DMA0 in the system control register (SYSR) are set to 01 by the CPU until they are cleared automatically by the Q2SD, operation will be unstable. When bits DMA1 and DMA0 are set to 11, the value in these registers is not referenced. Transfer data passes via the image data entry register (IDER), is converted, and stored sequentially starting at the data transfer start address indicated by the image data transfer start address register (ISAR). The address (A22 to A1) indicated by the DMASH and DMASL fields is a word address. Write 0 to bits that are not used for the DMASH and DMASL fields (a read will return an undefined value). The values of the DMASH and DMASL fields in the DMASR registers are initialized to all-0 by a reset. These registers are not incremented when DMA transfer is performed. Register Address: H'020
Bit 15 to 7 6 to 0 Bit Name Initial Value All 0 R/W R/W DMASH (address A22 to A16 setting) Description
Rev. 2.0, 09/02, page 263 of 366
Register Address: H'022
Bit 15 to 1 0 Bit Name Initial Value All 0 R/W R/W Description DMASH (address A15 to A1 setting)
5.6.2
DMA Transfer Word Count Registers (DMAWR)
The DMA transfer word count registers (DMAWR) specify the number of words (1 word = 16 bits) to be transferred in DMA transfer. If the value of these registers is modified during a series of DMA operations from the time bits DMA1 and DMA0 in the system control register (SYSR) are set to 01 or 11 by the CPU until they are cleared automatically by the Q2SD, operation will be unstable. When bits DMA1 and DMA0 are set to 11, the value in these registers is not referenced. Transfer data passes via the image data entry register (IDER), is converted, and stored sequentially starting at the data transfer start address indicated by the image data transfer start address register (ISAR). Write 0 to bits that are not used for the DMAWH and DMAWL fields (a read will return an undefined value). The values of the DMAWH and DMAWL fields in the DMAWR registers are initialized to all-0 by a reset. These registers are not decremented when DMA transfer is performed. Register Address: H'050
Bit 15 to 3 2 to 0 Bit Name Initial Value All 0 R/W R/W DMAWH Description
Register Address: H'054
Bit 15 to 0 Bit Name Initial Value All 0 R/W R/W Description DMAWL
Rev. 2.0, 09/02, page 264 of 366
5.6.3
Image Data Transfer Start Address Registers (ISAR)
The image data transfer start address registers (ISAR) specify the image data transfer destination as a physical address when the setting of bits YUV2, YUV1, and YUV0 is 001, 010, 011, or 111. The upper bits (A22 to A16) of the start address are set in the ISAH field, and the lower bits (A15 to A1) in the ISAL field. The address indicated by the ISAH and ISAL fields is a word address. If the value of these registers is modified during a series of data conversion operations from the time bits YUV2, YUV1, and YUV0 are set to 001, 010, 011, or 111 by the CPU until YUV mode is cleared automatically by the Q2SD, operation will be unstable. Write 0 to bits that are not used for the ISAH and ISAL fields. The values of the ISAH and ISAL fields in the ISAR registers are initialized to all-0 by a reset. These registers are not incremented when image data is transferred. Register Address: H'042
Bit 15 to 7 6 to 0 Bit Name Initial Value All 0 R/W R/W ISAH (address A22 to A16 setting) Description
Register Address: H'044
Bit 15 to 1 0 Bit Name Initial Value All 0 R/W R/W Description ISAL (address A15 to A1 setting)
Rev. 2.0, 09/02, page 265 of 366
5.6.4
Image Data Size Registers (IDSR)
The image data size registers (IDSR) specify the image data X size and Y size when the setting of bits YUV2, YUV1, and YUV0 is 001, 010, 011, or 111. For the image data X size, set the number of pixels when bits YUV2, YUV1, and YUV0 = 001, 010, or 011, and set 1/2 the number of pixels when bits YUV2, YUV1, and YUV0 = 111. An even number should be set for the X size (IDSX0 bit = 0). If the value of these registers is modified during a series of data conversion operations from the time bits YUV2, YUV1, and YUV0 are set to 001, 010, 011, or 111 by the CPU until YUV mode is cleared automatically by the Q2SD, operation will be unstable. Write 0 to bits that are not used for the IDSX and IDSY fields. The values of the IDSX and IDSY bits in the IDSR registers are initialized to all-0 by a reset. Register Address: H'046
Bit 15 to 11 10 to 0 Bit Name Initial Value All 0 R/W R/W IDSX* Description
Register Address: H'048
Bit 15 to 10 9 to 0 Bit Name Initial Value All 0 R/W R/W IDSY Description
Rev. 2.0, 09/02, page 266 of 366
5.6.5
Image Data Entry Register (IDER)
The image data entry register (IDER) comprises the entry in which image data is input when the setting of bits YUV2, YUV1, and YUV0 is 001, 010, 011, or 111. The IDER is initialized to H'0000 by a reset. Register Address: H'048
Bit 15 to 0 Bit Name Initial Value All 0 R/W W Description IDE
Rev. 2.0, 09/02, page 267 of 366
Rev. 2.0, 09/02, page 268 of 366
Section 6 Usage Notes
6.1 Power-On Sequence
The timing of the CLK0, CLK1, and RESET signals at power-on is shown in figure 6.1. Set 50 ms or less as the time from the rising edge of VCCn to the rising edge of CLK0/CLK1, and 100 ms or more as the time from the rising edge of VCCn to the rising edge of RESET. If CLK0 and CLK1 are halted for a long time (50 ms or more) after powering on, the device may be permanently damaged.
VCC min V ILT VCC Less than 50 ms
VIHC CLK0, CLK1
Min. 100 ms
VILT
Figure 6.1 Power-On Sequence
Rev. 2.0, 09/02, page 269 of 366
6.2
Use of 64-Mbit SDRAM (x16 Type)
The Q2SD references the value of bits MES1 and MES0 in the memory mode register (MMR) following the elapse of 70 tcyc0 after a hardware reset, and makes the UDQM1 pin the MA13 signal output pin if MES1 and MES0 = B10, or the upper word upper byte input/output mask signal output pin if MES1 and MES0 = B00. If the setting of MES1 and MES0 has not been carried out by this time, the values of MES1 and MES0 cleared by a hardware reset will be referenced. Therefore, only when using the MES1 and MES0 = 1, 0 mode (64-Mbit (x16) memory size, one memory used, 16-bit bus), the MES1, MES0 = 1, 0 setting must be made before the elapse of 70 tcyc0 after a hardware reset.
Rev. 2.0, 09/02, page 270 of 366
6.3
CPU Interface Unit FIFO
The Q2SD stores the display list which is sent from the CPU to the UGM via a 16-word on-chip FIFO. The CPU gives the rendering start instruction to the Q2SD after the transfer of display list. However, note that when the rendering start address is within the last 16-word data at the end of the display list, the Q2SD may fetch the previous fetch-starting data on the UGM before the completion of flushing the FIFO caused by the start of rendering. To avoid the such previous data from being fetched, CPU must perform UGM dummy read after the display list transfer, and give instruction to start rendering to the Q2SD. * Rendering start bit (RS) When RS is set to 1, starts fetching the data (display list) on the UGM from the address that is shown by the display list start address register (DLASR). * Display list start address register (DLSAR) Register that stores the display list fetching start address.
Rev. 2.0, 09/02, page 271 of 366
6.4
Video Fetching Start Timing
Data is captured at the timing of detecting two rising edges of the VHS signal after detecting VVS = 1 and VHS = 1. The VQCLK must be input only for necessary data.
A
B
VQCLK VIN 1H line period Video data is not incorporated. VQCLK is ignored. Details: VHS high period Video data is incorporated.
tVHS tVOS
Figure 6.2 Video Interface Timing
6.5
Drawing Using Linear Format Source
When the POLYGON4A, POLYGON4B, PLINE, or RPLINR command is executed with linear format source specified, there is the following restriction regarding the size in the X direction of the linear format source. If a command is executed ignoring the restriction, the error drawing (dot) absence may occur. Use the above commands within the following restrictions.
Rev. 2.0, 09/02, page 272 of 366
Marking Specifications Product Type HD64413AF HD64413AFI HD64413ASF HD64413ASFI Marking Type No. HD64413AF HD64413AFI HD64413AF HD64413AFI Mask Code None None S S
Source X Direction Maximum Size 1 Bit/Pixel BYTE 1 to 32 1 to 32 1 to about 128 1 to about 128 TDX (pixel) 8 to 256 8 to 256 8 to 1023 8 to 1023 8 Bits/Pixel BYTE 8 to 32 8 to 32 8 to 1023 8 to 1023 TDX (pixel) 8 to 32 8 to 32 8 to 1023 8 to 1023 16 Bits/Pixel BYTE 16 to 32 16 to 32 8 to 1023 8 to 1023 TDX (pixel) 8 to 16 8 to 16 8 to 1023 8 to 1023
Note: TDX: Source X direction size (pixel) Products with restrictions: HD64413AF, HD64413AFI Products with no restrictions: HD64413ASF, HD64413ASFI
6.6
SDRAM Mode Register Values for UGM Set by Q2SD
Initial sequence is executed in order to set the mode register in the SDRAM which is connected as the UGM that is set by the Q2SD. The SDRAM that is used for the UGM must support the following functions that are set by the Q2SD. The mode register settings in the SDRAM are the following fixed values. Please keep in mind that those values depend on mask version of the Q2SD.
Rev. 2.0, 09/02, page 273 of 366
Type No. HD64413AF*
4
Marking No. HD64413AF
Process Code None
Mask Code None
SDRAM Operating Mode Set by the Q2SD Burst read & burst write mode, CAS latency * 3, burst type is sequential, 1 burst length * 1* Burst read & burst write mode, CAS latency * 3, burst type is sequential, 1 burst length * 1* Burst read & single write mode, CAS latency * 3, burst type is sequential, 23 burst length * 1* * Burst read & single write mode, CAS latency * 3, burst type is sequential, 23 burst length * 1* *
HD64413AF*
4
HD64413AF
I
None
HD64413ASF
HD64413AF
None
S
HD64413ASFI
HD64413AF
I
S
Notes: 1. SDRAM mode register value set by the Q2SD is H'2030. When a single SRAM with the memory capacity of 64 Mbits and data width of 16 bits is used, select a product which the SRAM mode register bit that corresponds to Q2SD MA13 is "don't care". 2. SDRAM mode register value set by the Q2SD is H'2230. When a single SRAM with the memory capacity of 64 Mbits and data width of 16 bits is used, select a product which the SRAM mode register bit that corresponds to Q2SD MA13 is "don't care". 3. Normal operation can be performed by the following SDRAM even though they do not support the burst read & single write mode: MSM56V16160F (Oki Electric Industry Co., Ltd., 2-bank x 512-kword x 16-bit SDRAM F version) 4. The production of the HD64413AF and the HD64413AFI will be discontinued after the HD64413ASF and the HD64413ASFI start mass production.
Rev. 2.0, 09/02, page 274 of 366
Section 7 Electrical Characteristics
7.1
Table 7.1
Item Power supply voltage Input voltage Permissible output low current Total permissible output low current Permissible output high current Total permissible output high current Operating temperature Storage temperature
Absolute Maximum Ratings
Absolute Maximum Ratings
Symbol VCC * Vin *
1 2 3 2 3 1
Value -0.3 to +4.6 -0.3 to VCC +0.3 2 172 2 172 0 to 70 -55 to +125
Unit V V mA mA mA mA C C
| IoL | *
| IoL | *
| -IoH | * Topr Tstg
| (-IoH) | *
Notes: 1. Value based on GND = 0 V. Includes DAVCC and PLLVCC. 2. The permissible output current is the maximum value of the current drawn in or flowing out from one output pin and one input/output pin. 3. The total permissible output current is the sum of currents drawn in or flowing out from output pins and input/output pins.
Caution: Permanent damage to the chip may result if absolute maximum ratings are exceeded. In normal operation, it is advisable to observe the recommended operating conditions. Exceeding these conditions may adversely affect the reliability of the chip.
7.2
Table 7.2
Item
Recommended Operating Conditions
Recommended Operating Conditions
Symbol VCC* VILT*
1 1 1 1 1
Min 3.0 0 0 2.2 0.8VCC 0
Typ 3.3 25
Max 3.6 0.6 0.6 VCC VCC 70
Unit V V V V V C
Power supply voltage Input low voltage (except CLK0, CLK1) Input low voltage (CLK0, CLK1) Input high voltage (except CLK0, CLK1) Input high voltage (CLK0, CLK1) Operating temperature
VILC*
VIHT* Topr*
VIHC*
2
Notes: 1. Value based on GND = 0 V. 2. For details on the product with the operating temperature of -40C to 85C, please contact your Hitachi sales agency. Rev. 2.0, 09/02, page 275 of 366
7.3
7.3.1
Electrical Characteristics Test Methods
Timing Testing
The output low voltage for timing testing is 1.5 V. The output high voltage for timing testing is 1.5 V.
V VOL for timing testing VOH DC level (steady) VOL
0
Reference point
t
Figure 7.1 Basis of VOL Timing Testing
Rev. 2.0, 09/02, page 276 of 366
7.3.2
Test Load Circuit (All Output and Input/Output Pins)
V
RL Test point V = 3.3 V RL = 2 k C = 60 pF R = 11 k All diodes are Hitachi 1S2074 equivalent products.
C
R
Input/output timing test levels (excluding CLK0 and CLK1) Low level: 1.5 V High level: 1.5 V
Figure 7.2 Test Load Circuit
Rev. 2.0, 09/02, page 277 of 366
7.4
7.4.1
Electrical Characteristics
DC Characteristics DC Characteristics
Table 7.3
Unless otherwise indicated, VCC = DACVCC = PLLVCC = 3.3 V 0.3 V, GND = DACGND = PLLGND = 0 V, Ta = 0 to +70C. Each value listed below is target one. Some values are reflected the result of the test of sample chips.
Item Input high voltage (CMOS level) Input low voltage (CMOS level) Input high voltage (TTL level) Input low voltage (TTL level) Input leakage current Three-state leakage current (off state) Output high voltage Output low voltage Input capacitance I1, I2 IO, O IO, O IO, O IO I1, I2 Current consumption ICC I2, IO Pin Names Symbol I1 VIHC VILC VIHT VILT Iin ITSI VOH VOL Cin Min 0.8 x VCC -0.3 2.2 -0.3 2.2 Max Unit Test Conditions
VCC + 0.3 V VCC x 0.2 VCC + 0.3 V VCC x 0.2 1 1 0.6 20 20 350 mA pF V A Vin = 0 - VCC Vin = 0.4 - VCC IOH = -200 A IOL = 1.6 mA Vin = 0 V Ta = 25C f = 1.0 MHz Data bus operating/display operating/ command being executed
Note: The symbols used in table 7.3 are explained below.
Rev. 2.0, 09/02, page 278 of 366
Symbol I1 I2
Input CMOS TTL
Output
High-Z
Pull-up
Pin Names CLK0, CLK1 MOD2 to MOD0, 5(6(7, A22 to A1, &6, &6, 5', :(, :(, '$&., VIN7 to VIN0, 9+6 996, 92'', VQCLK D15 to D0, +6<1&/(;+6<1&,
96<1&/(;96<1&, 2''),
IO
TTL
CMOS
Yes
MD31 to MD0 O CMOS
'5(4, :$,7, ,5/, &6<1&, DISP, CDE, MA13 to MA0, 0&6, 0:(, 05$6, 0&$6, LDQM1, LDQM0, UDQM1, UDQM0, MCLK
Rev. 2.0, 09/02, page 279 of 366
7.4.2 Clocks
AC Characteristics
Table 7.4
Input Clocks (Pins MODE2 to MODE0 = 000, 001, or 010: Multiplication On)
Unless otherwise indicated, VCC = DACVCC = PLLVCC = 3.3 V 0.3 V, GND = DACGND = PLLGND = 0 V, Ta = 0 to +70C. Each value listed below is target one. Some values are reflected the result of the test of sample chips.
Item CLK0 cycle time 1 CLK0 cycle time 2 CLK0 cycle time 3 CLK0 high pulse width CLK0 low pulse width MCLK cycle time MCLK high pulse width MCLK low pulse width CLK1 cycle time CLK1 high pulse width CLK1 low pulse width CLK1 duty CLK1 rise time CLK1 fall time MCLK rise time MCLK fall time Symbol tcyc tcyc tcyc tCPWH tCPWL t cyc0 tCMPWH tCMPWL tcyc1 tC1PWH tC1PWL tC1DT tcr tcf tmcr tmcf Min 15 30 60 5.5 5.5 15 5.0 5.0 30 10 10 0.5tcyc1 - 0.07tcyc1 Max 25 50 100 25 200 0.5tcyc1 + 0.07tcyc1 5.0 5.0 4.5 4.5 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions Figure 7.3 Notes x1 x2 x4
Reset Table 7.5
Item
5(6(7
Reset
Symbol Min 40 Max Unit tcyc0 Test Conditions Figure 7.4 Notes
low pulse width
tRESW
Rev. 2.0, 09/02, page 280 of 366
CPU Read Cycle Table 7.6
Item Address setup time Address hold time
&6Q &6Q
CPU Read Cycle
Symbol tADS tADH tCSS tCSH tWAS1 tRDHW tRDDWS tWAD tRDDON tRDDH tRDDOF tWEHW Min 0 0 0 0 tcyc0 0 tcyc0 0 1.5 1.5 tcyc0 Max 3tcyc0 + 15 Unit ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions Figure 7.5 1 2 3 Notes
setup time hold time cycle start time 1
:$,7 5'
high width
Read data setup time with respect to :$,7
:$,7
drive time
Read data turn-on time Read data hold time Read data turn-off time
:(
high width
Notes: 1. Address signals A22 to A1 must be held at least until the rise of :$,7. 2. If the fall of &6Q is later than the fall of 5', the specifications for tADS, tWAS1, tRDDON, and tWEHW are from the fall of &6Q. &6Q = &6, &6. 3. If the rise of &6Q is earlier than the rise of 5', the specifications for tADH, tRDDH, tRDDOF, and tWEHW are from the rise of &6Q. &6Q = &6, &6.
Rev. 2.0, 09/02, page 281 of 366
CPU Write Cycle Table 7.7
Item Address setup time Address hold time
&6Q &6Q 5'
CPU Write Cycle
Symbol tADS tADH tCSS tCSH tRDHW tWAD tWAS2 tWEHW tWRDES tWRDH Min 0 2 0 0 tcyc0 tcyc0 tcyc0 2tcyc0 2 Max 3tcyc0 + 15 Unit ns ns ns ns ns ns ns ns ns ns 3 3 1 2 Test Conditions Figure 7.6 Notes
setup time hold time drive time cycle start time 2
high width
:$,7 :$,7 :(
high width
Write data setup time with respect to :( Write data hold time
Notes: 1. If the fall of &6Q is later than the fall of :(Q, the specifications for tADS, tRDHW, and tWAS2 are from the fall of &6Q. &6Q = &6, &6; :(Q = :(, :(. 2. If the rise of &6Q is earlier than the rise of :(Q, the specifications for tADH, tRDHW, tWRDES, tWRDH, and tWRDOF are from the rise of &6Q. &6Q = &6, &6; :(Q = :(, :(. 3. :(Q = :(, :(.
Rev. 2.0, 09/02, page 282 of 366
DMA Write Cycle Table 7.8
Item
5' 5' :(
DMA Write Cycle
Symbol tRDHW tRDLW tWEHW tWRDH tWRDRS tDARN tDARA tDARS tDARH tDAWS tDAWH tWELW tWRDWS tWRDWH tDAWN tDAWA Min tcyc0 3tcyc0 tcyc0 2 2tcyc0 3tcyc0 + 15 0 0 0 0 3tcyc0 2tcyc0 2 3tcyc0 + 15 Max 3tcyc0 + 15 3tcyc0 + 15 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions Figure 7.7 (1), (2), (3), (4) Notes
high width low width high width
Write data hold time Write data setup time with respect to 5' negate time with respect to 5'
'5(4
assert time with respect to 5'
'5(4
setup time with respect to 5'
'$&.
hold time with respect to 5'
'$&.
setup time with respect to :(
'$&.
hold time with respect to :(
'$&. :(
low width
Write data setup time with respect to :( Write data hold time with respect to :( negate time with respect to :(
'5(4
hold time with respect to :(
'5(4
Notes: 1. If the fall of '$&. is later than the fall of 5', the specification for tRDLW is from the fall of '$&.. 2. If the rise of '$&. is earlier than the rise of 5', the specifications for tRDLW, tWRDH, and tWRDRS are from the rise of '$&.. 3. If the fall of '$&. is later than the fall of :(Q, the specification for tWELW is from the fall of '$&.. :(Q = :(, :(. 4. If the rise of '$&. is earlier than the rise of :(Q, the specifications for tWELW, tWRDWS, and tWRDWH are from the rise of '$&.. :(Q = :(, :(.
Rev. 2.0, 09/02, page 283 of 366
Interrupt Output Table 7.9
Item
,5/
Interrupt Output
Symbol tIRD Min Max 15 Unit ns Test Conditions Figure 7.8 Notes
delay time
UGM Read Cycle Table 7.10 UGM Read Cycle
Item MD input setup time MD input hold time MD input turn-on time MD input turn-off time MA delay time MA hold time MD output turn-off time MD output turn-on time MCS delay time MCS hold time Symbol tMDIS tMDIH tMDIN tMDIF tMAD tMAH tMDOF tMDON tMCSD tMCSH Min 6 3 0 1 0 1 Max 9 12 12 12 Unit ns ns ns ns ns ns ns ns ns ns Test Conditions Figure 7.9 Notes
UGM Write Cycle Table 7.11 UGM Write Cycle
Item MD output delay time MD output hold time MA delay time MA hold time MCS delay time MCS hold time Symbol tMDOD tMODH tMAD tMAH tMCSD tMCSH Min 1 1 1 Max 12 12 12 Unit ns ns ns ns ns ns Test Conditions Figure 7.10 Notes
Rev. 2.0, 09/02, page 284 of 366
UGM Refresh Cycle/Mode Register Setting Cycle Table 7.12 UGM Refresh Cycle/Mode Register Setting Cycle
Item MA delay time MA hold time MCS delay time MCS hold time Symbol tMAD tMAH tMCSD tMCSH Min 1 1 Max 12 12 Unit ns ns ns ns Test Conditions Figure 7.11 (1), (2) Notes
Master Display Mode Table 7.13 Master Display Mode
Item
+6<1& 96<1& 2'')
Symbol delay time from CLK1 delay time from CLK1 delay time from CLK1 tHSDD tVSDD tODDD tSYDD tDIDD tCDEDD
Min
Max 15 15 15 15 15 15
Unit ns ns ns ns ns ns
Test Conditions Figure 7.12
Notes
delay time from CLK1
&6<1&
DISP delay time from CLK1 CDE delay time from CLK1
Rev. 2.0, 09/02, page 285 of 366
TV Sync Display Mode Table 7.14 TV Sync Display Mode
Item DISP delay time from CLK1 CDE delay time from CLK1
(;+6<1& (;+6<1& (;+6<1&
Symbol tDIDD tCDEDD tEXLLW tEXHHW tEXH1 tEXH2 tDIEXH tEXVLW tEXV1 tEXV2 tOD1 tOD2
Min 4tcyc1 4tcyc1 5 5 hds - 1 3HC 5 5 (ys + yw) x HC 1tcyc1
Max 15 15 hds - 1
Unit ns ns ns ns ns ns tcyc1 tcyc1 ns ns tcyc1 ns
Test Conditions Figure 7.13 (1), (2)
Notes
low width high width
reception undefined time 1 reception undefined time 2
(;+6<1&
DISP start time with respect to (;+6<1&
(;96<1& (;96<1&
*
low width
reception undefined time 1 reception undefined time 2
(;96<1& 2'')
reception undefined reception undefined * hds = hsw + xs
time 1
2'')
time 2 Note:
Rev. 2.0, 09/02, page 286 of 366
Video Interface Table 7.15
Item VQCLK high pulse width VQCLK low pulse width
92''
Video Interface
Symbol tQHW tQLW tVOS tVNS tVNH tVVL tVHL tQQP tVOH tVHS THQS Min 15 15 1 5 11.7 2 64 34.5 1 5 10 2 Max Unit ns ns tcyc0 ns ns Hline tcyc0 ns tcyc0 tcyc0 tcyc0 Hline * tQQP > 2 x tcyc0 * Test Conditions Figure 7.14 (1), (2) Notes
setup time
VIN setup time VIN hold time
996 9+6
low pulse width low pulse width
VQCLK rise--VQCLK rise interval
92'' 996 9+6 9+6
hold time
setup time setup time *
reception undefined time tVHSRU Hline is the 9+6 cycle.
Note:
Video DAC Table 7.16
Item Resolution Differential linearity error Conversion speed Maximum output current Analog full-scale output Analog zero-scale output Full-scale error Iout 0.9 -0.1 -10
Video DAC
Symbol Min 8 Max 8 0.5 33 3 1.1 0.1 10 Unit Bit LSB MHz mA V V % DC test DC test DC test Test Conditions DC test DC test Data write test Notes
Rev. 2.0, 09/02, page 287 of 366
7.5
7.5.1
Timing Charts
Clocks
tCPWH VIH 0.5VCC VIH 0.5VCC VIL VIL tCPWL
0.5VCC
CLK0 (input) (pins MODE2 to MODE0 = 000)
tcyc
tmcr
tCMPWH
tmcf
tCMPWL VOH 0.5VCC VOH
VOH 0.5VCC VOH MCLK (output) (pins MODE2 to MODE0 = 000, 001, 010) tcr
VOH 0.5VCC VOH tcyc0
tC1PWH VIH 0.5VCC VIL tC1DT
tcf
tC1PWL VIH 0.5VCC VIL tC1DT
VIH 0.5VCC CLK1 (input) (pins MODE2 to MODE0 = 000, 001, 010) VIL
tcyc1
Figure 7.3 Input Clocks 7.5.2 Reset Timing
tRESW (input)
Figure 7.4 Reset Timing
Rev. 2.0, 09/02, page 288 of 366
7.5.3
tADS
tADH
A22 to A1 (input) tCSS tCSH
to (input) tRDHW tRDHW
CPU Read Cycle Timing
(input) tWEHW tWEHW
to (input) tWAS1 tWAD
(output) tRDDON tRDDWS
tRDDH tRDDOF
D15 to D0 (input/output)
Figure 7.5 CPU Read Cycle Timing (CPU Q2SD) with Hardware Wait
High (cannot be low simultaneously with / )
Rev. 2.0, 09/02, page 289 of 366
(input)
7.5.4
tADS tADH
A22 to A1 (input) tCSS tCSH
Rev. 2.0, 09/02, page 290 of 366
tRDHW tRDHW tWEHW tWEHW tWAS2 tWAD tWRDH tWRDES High (cannot be low simultaneously with / )
CPU Write Cycle Timing
to (input)
(input)
to (input)
(output)
D15 to D0 (input/output)
Figure 7.6 CPU Read Cycle Timing (CPU Q2SD) with Hardware Wait
(input)
7.5.5
tDARS tDARH
(input)
to (input)
High (cannot be low simultaneously with )
tRDHW tRDLW
tRDHW
(input) tWRDRS tWRDH
DMA Write Cycle Timing (DMAC Q2SD)
D15 to 0 (input/output) (DDA1 = 0, DDA0 = 1)
High
(output) tWRDRS
tWRDH
D15 to D0 (input/output) (DDA1 = 0, DDA0 = 1)
Figure 7.7 (1) DMA Write Cycle Timing (Single Address, DMAC Q2SD)
High (cannot be low simultaneously with )
Rev. 2.0, 09/02, page 291 of 366
to (input)
tDARA
tRDHW
)
High (cannot be low simultaneously with
tDARN
(output)
(input)
to
tDARS (input)
Figure 7.7 (2) DMA Write Cycle Timing (Single Address, DMAC Q2SD)
Rev. 2.0, 09/02, page 292 of 366
tDARH
tDAWS (input) tWEHW to (input) tWELW tWEHW
tDAWH
(input)
High (cannot be low simultaneously with
/
) High
(output) tWRDWS D15 to D0 (input/output)
tWRDWH
Figure 7.7 (3) DMA Write Cycle Timing (Dual Address, DMAC Q2SD)
(input)
Rev. 2.0, 09/02, page 293 of 366
tDAWA tWEHW
High (cannot be low simultaneously with to (input) (input)
tDAWN
/ (output) tDAWS (input)
Figure 7.7 (4) DMA Write Cycle Timing (Dual Address, DMAC Q2SD)
Rev. 2.0, 09/02, page 294 of 366
tDAWH
)
7.5.6
Interrupt Output Timing
tIRD
tIRD
Figure 7.8 Interrupt Output Timing
MCLK
(output)
Rev. 2.0, 09/02, page 295 of 366
, " !
7.5.7 UGM Read Cycle Timing
MCLK tMCSD tMCSH (output) tMCSD tMCSD tMCSD tMCSD tMCSH tMCSH tMCSH tMCSH (output) tMCSD tMCSD tMCSH tMCSD tMCSH tMCSH (output) tMCSD tMCSD tMCSD tMCSH tMCSH tMCSH (output) tMAD tMAH MA11 (output) MA10 (output) MA9 (output) MA8 (output) MA7 to MA0 (output) tMCSD tMCSH LDQM0, LDQM1, UDQM0, UDQM1 (output) MD31 to MD0 (input/output) tMDOF tMDIS tMDIH tMDON tMDIN tMDIF
Figure 7.9 UGM Read Cycle Timing
Rev. 2.0, 09/02, page 296 of 366
, " !
7.5.8 UGM Write Cycle Timing
MCLK tMCSD tMCSH (output) tMCSD tMCSD tMCSD tMCSD tMCSH tMCSH tMCSH tMCSH (output) tMCSD tMCSD tMCSH tMCSD tMCSH tMCSH (output) tMCSD tMCSD tMCSH tMCSD tMCSH tMCSD tMCSD tMCSH tMCSH tMCSH (output) tMAD tMAH MA11 (output) MA10 (output) MA9 (output) MA8 (output) MA7 to MA0 (output) tMCSD tMCSH LDQM0, LDQM1, UDQM0, UDQM1 (output) MD31 to MD0 (input/output) tMDOD tMDOH
Figure 7.10 UGM Write Cycle Timing
Rev. 2.0, 09/02, page 297 of 366
7.5.9
UGM Refresh Cycle Timing and Mode Register Setting Timing
, ! !
MCLK tMCSD tMCSH (output) tMCSD tMCSH (output) tMCSD tMCSH (output) tMCSD tMCSH (output) MA11 to MA0 (output) LDQM0, LDQM1, UDQM0, UDQM1 (output) MD31 to MD0 (input/output)
Figure 7.11 (1) UGM Refresh Cycle Timing
Rev. 2.0, 09/02, page 298 of 366
Figure 7.11 (2) UGM Mode Register Setting Cycle Timing
, ! !
MCLK tMCSD tMCSH (output) tMCSD tMCSH (output) tMCSD tMCSH (output) tMCSD tMCSH (output) tMAD tMAH MA11 to MA0 (output) LDQM0, LDQM1, UDQM0, UDQM1 (output) MD31 to MD0 (input/output)
Rev. 2.0, 09/02, page 299 of 366
7.5.10
Master Mode Display Timing
T1 CLK1 (input) T1 T1
R,G,B (output)
tHSDD (output) tVSDD (output)
tHSDD
tVSDD
tODDD (output) tSYDD (output)
tODDD
tSYDD
tDIDD DISP (output)
tDIDD
tCDEDD CDE (output)
tCDEDD
Figure 7.12 Master Mode Display Timing
Rev. 2.0, 09/02, page 300 of 366
7.5.11
TV Sync Mode Display Timing
T1 CLK1 (input) T1 T1
R,G,B (output)
tDIDD DISP (output)
tDIDD
tCDEDD CDE (output)
tCDEDD
High (output)
Figure 7.13 (1) TV Sync Mode Display Timing
Rev. 2.0, 09/02, page 301 of 366
1tcyc1
CLK1 (input)
tEXHHW tEXLLW (input) tEXV1 tEXVLW (input) tOD2
Rev. 2.0, 09/02, page 302 of 366
tEXH1 tEXH2 tEXH1 tEXV2 tOD1 tDIEXH tDIDD
(input)
Figure 7.13 (2) TV Sync Mode Display Timing
CLK1 (input)
R,G,B (output)
DISP (output)
7.5.12
Video Interface Timing
tQQP tQHW tQLW
VQCLK tVNS VIN[7:0] tVNH
Figure 7.14 (1) Video Interface Timing
tVVL
tVHS tVHL tVHSRU tVOS tVOH
tHQS VQLK While or is a low level, or during tVHS and tHQS, or tVHSRU, VQCLK must not be input.
Figure 7.14 (2) Video Interface Timing
Rev. 2.0, 09/02, page 303 of 366
Rev. 2.0, 09/02, page 304 of 366
Register Address Abbreviation
15 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 TVCL FRCL DMCL CECL VBCL TRCL CSCL 0 0 0 0 0 0 0 0 0 0 1 1 0 14 13 12 11 10 9 8 5 4 3 2 1 0 SYSR SR SRCR IER MEMR DSMR REMR IEMR DMASR DMAWR ISAR 0 0 0 0 0 IDSR 0 0 0 0 0 0 0 1 1 0 0 IDER DMAWR DSMR2 VIMR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCM1 SCM0 MWX 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GBM2 GBM1 GBM0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 6 0 DBM1 DBM0 DBF 0 1 BRCL 0
A [10:0]
R/W
Data
Register Name
Table A.1
1
0
000 002 004 006 008 00A 00C 00E 020 022 024 042 044 046 048 04A 050 056 072 CSY1 CSY0 0 0
System control
R/W R W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W R/W R/W R/W
Status Status register clear Interrupt enable Memory mode Display mode Rendering mode Input data conversion mode H DMA transfer start address L DMA transfer word count L Image data transfer start H address L X Image data size Y Image data entry H DMA transfer word count Display mode 2 Video incorporation mode
Initial Register Values after Hardware Reset
Appendix A Initial Register Values
Only bits marked
are affected by a reset. Registers other than those shown above are not affected by a reset.
Rev. 2.0, 09/02, page 305 of 366
Appendix B Commands and Parameters
B.1 Relationship between Commands and Rendering Attributes
Relationship between Commands and Rendering Attributes
Reference Data
Multi-Valued Source
Table B.1
Drawing Destination
Rendering Attributes
Line drawing edge Bold Line Drawing
Binary Work
Command
Specified Color
Binary Source
Rendering
WORK
POLYGON4A POLYGON4B POLYGON4C LINE RLINE PLINE RPLINE FTRAP RFTRAP CLRW LINEW RLINEW MOVE RMOVE LCOFS RLCOFS CLIP WPR JUMP GOSUB RET NOP3 VBKEM TRAP
O O
A A A O O O O O
O O O O O O O O O O V V O O
* O
* O
O O O O O
* O * O O O O
* O * O O O O B B
* O * O O
O
*
Z O
O
COOF
TRNS
HALF
STYL
Work
CLIP
EDG
EOS
NET
REL
FST
LNi
O O
O O
O O O O O O O
O O O O
O O
O O
O: Can be used V: Can be used (specified color is binary EOS bit value) A: Referenced depending on mode (valid when WORK = 1) B: Referenced depending on mode (valid when EDG = 1) *: Referenced depending on mode (clear to 0 when FST = 1) Z: Referenced depending on mode (clear to 0 when LNi = 1) Blank: Cannot be used (clear to 0) : Can be used with restriction, HALF: x < 0 is prohibited, COOF: miniaturization is prohibited.)
Rev. 2.0, 09/02, page 306 of 366
B.2
Command Codes
Command Codes
15 CODE DRAW MODE 0
Table B.2
CODE 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0
COMMAND POLYGON4A POLYGON4B POLYGON4C FTRAP RFTRAP LINEW RLINEW LINE RLINE PLINE RPLINE MOVE RMOVE LCOFS RLCOFS CLRW UCLIP WPR SCLIP JUMP GOSUB VBKEM RET TRAP NOP3
Rev. 2.0, 09/02, page 307 of 366
B.3
Command Parameter Specifications
Note that words of the command code are omitted.
Rev. 2.0, 09/02, page 308 of 366
POLYGON4 Commands
: Fixed at 0
15 TXS or TYS 0
Source starting point TXS or TYS Given as unsigned max. 10-bit data. Specify correctly according to source area size.
0
15 TDX or TDY
Source size TDX or TDY Given as unsigned max. 10-bit data. TDX can only be set in 8-pixel units.
0
15 SOURCE ADDRESS H 15 SOURCE ADDRESS L
1-bit/pixel source start upper address Given as upper 10 bits.
0
1-bit/pixel source start lower address Given as lower 13 bits. Source address is set as a byte address.
0
15 Sign extension
Sign
RELATIVE SOURCE ADDRESS H
Source start relative upper address Given as upper 10 bits. Use sign extension in upper vacant bits. Source start relative lower address Given as lower 13 bits.
15 RELATIVE SOURCE ADDRESS L
0
15
12 11 10
Sign
0 DXn or DYn
Sign extension
Rendering, work coordinate Vertex coordinate DXn or DYn (1 n 4) Given as signed 12-bit data. Use sign extension in upper vacant bits. 16-bit/pixel color specification Color data 0 given as 16-bit data.
15 COLOR0
0
15 COLOR1 or COLOR
0
16-bit/pixel color specification Color data 1 given as 16-bit data.
0
15 COLOR0 15 COLOR1 or COLOR COLOR1 or COLOR COLOR0
8-bit/pixel color specification Color data 0 given as repeated 8-bit data.
0
8-bit/pixel color specification Color data 1 given as repeated 8-bit data.
Rev. 2.0, 09/02, page 309 of 366
FTRAP, RFTRAP
15 n 0
Number of vertices (2 n 65,535), absolute (1 n 65,535), relative Given as unsigned 16-bit data.
15
12 11 10
Sign
0 DXL
Sign extension
Left-hand side coordinate DXL Given as signed 12-bit data. Use sign extension in upper vacant bits.
0
15
12 11 10
Sign
Sign extension
DXn
Absolute coordinate Vertex coordinate DXn (2 n 65,535) Given as signed 12-bit data. Use sign extension in upper vacant bits.
0
15
12 11 10
Sign
Sign extension
DYn
Absolute coordinate Vertex coordinate DYn (2 n 65,535) Given as signed 12-bit data. Use sign extension in upper vacant bits.
0
15
Sign
DXn
Sign
DYn
Relative coordinates Vertex coordinates DXn, DYn (1 n 65,535) Given as signed 8-bit data.
LINEW, RLINEW
15 n 0
Number of vertices (2 n 65,535), absolute (1 n 65,535), relative Given as unsigned 16-bit data.
15
12 11 10
Sign
0 DXn
Sign extension
Absolute coordinate Vertex coordinate DXn (2 n 65,535) Given as signed 12-bit data. Use sign extension in upper vacant bits.
0
15
12 11 10
Sign
Sign extension
DYn
Absolute coordinate Vertex coordinate DYn (2 n 65,535) Given as signed 12-bit data. Use sign extension in upper vacant bits.
0
15
Sign
DXn
Sign
DYn
Relative coordinates Vertex coordinates DXn, DYn (1 n 65,535) Given as signed 8-bit data.
Rev. 2.0, 09/02, page 310 of 366
CLRW
15 12 11 10
Sign
0 XMIN or XMAX
Sign extension
Left and right X coordinates XMIN, XMAX Given as unsigned 12-bit data.
15
12 11 10
Sign
0 YMIN or YMAX
Sign extension
Upper and lower Y coordinates YMIN, YMAX Given as signed 12-bit data.
LINE, RLINE
15 n 0
Number of vertices (2 n 65,535), absolute (1 n 65,535), relative Given as unsigned 16-bit data.
0
15 LINE COLOR0
16-bit/pixel color specification Color data given as 16-bit data.
15 LINE COLOR LINE COLOR
0
8-bit/pixel color specification Color data given as repeated 8-bit data.
15
12 11 10
Sign
0 DXn
Sign extension
Absolute coordinate Vertex coordinate DXn (2 n 65,535) Given as signed 12-bit data. Use sign extension in upper vacant bits.
0
15
12 11 10
Sign
Sign extension
DYn
Absolute coordinate Vertex coordinate DYn (2 n 65,535) Given as signed 12-bit data. Use sign extension in upper vacant bits.
0
15
Sign
DXn
Sign
DYn
Relative coordinates Vertex coordinates DXn, DYn (1 n 65,535) Given as signed 8-bit data.
Rev. 2.0, 09/02, page 311 of 366
PLINE, RPLINE
: Fixed at 0
15 LINE COLOR0 0
16-bit/pixel color specification Color data given as 16-bit data.
15 LINE COLOR LINE COLOR
0
8-bit/pixel color specification Color data given as repeated 8-bit data.
15 SOURCE ADDRESS H
0
1-bit/pixel source start upper address Given as upper 10 bits.
15 SOURCE ADDRESS L
0
1-bit/pixel source start lower address Given as lower 13 bits. Source address is set as a byte address.
0
15 n
Number of vertices (2 n 65,535), absolute (1 n 65,535), relative Given as unsigned 16-bit data.
0
15 LPPT TDX
Source size TDX Line pattern pointer LPPT Given as unsigned max. 10-bit data. TDX can only be set in 8-pixel units.
0
15
12 11 10
Sign
Sign extension
DXn
Absolute coordinate Vertex coordinate DXn (2 n 65,535) Given as signed 12-bit data. Use sign extension in upper vacant bits.
0
15
12 11 10
Sign
Sign extension
DYn
Absolute coordinate Vertex coordinate DYn (2 n 65,535) Given as signed 12-bit data. Use sign extension in upper vacant bits.
0
15
Sign
DXn
Sign
DYn
Relative coordinates Vertex coordinates DXn, DYn (1 n 65,535) Given as signed 8-bit data.
Rev. 2.0, 09/02, page 312 of 366
MOVE, RMOVE
15 12 11 10
Sign
0 XC
Sign extension
Absolute coordinate Vertex coordinate XC Given as signed 12-bit data. Use sign extension in upper vacant bits.
0
15
12 11 10
Sign
Sign extension
YC
Absolute coordinate Vertex coordinate YC Given as signed 12-bit data. Use sign extension in upper vacant bits.
0
15
Sign
XC
Sign
YC
Relative coordinates Vertex coordinates XC, YC Given as signed 8-bit data.
LCOFS, RLCOFS
15 12 11 10
Sign
0 XO or YO
Sign extension
Relative specification Local offset value XO or YO Given as signed 12-bit data. Use sign extension in upper vacant bits.
0
15
Sign
XO
Sign
YO
Relative specification Local offset values XO, YO Given as signed 8-bit data.
UCLIP, SCLIP
: Fixed at 0
15 XMIN, XMAX 0
Left and right X coordinates XMIN, XMAX Given as unsigned 10-bit data.
15 YMIN, YMAX
0
Upper and lower Y coordinates YMIN, YMAX Given as unsigned 9-bit data.
Rev. 2.0, 09/02, page 313 of 366
JUMP
: Fixed at 0
15 JUMP ADDRESS H 0
Jump destination upper address Given as upper 10 bits.
15 JUMP ADDRESS L
0
Jump destination lower address Given as lower 13 bits. Jump destination address is set as an even byte address.
0
15 Sign extension
Sign
RELATIVE JUMP ADDRESS H
Relative jump destination upper address Given as upper 10 bits. Use sign extension in upper vacant bits.
15 RELATIVE JUMP ADDRESS L
0
Relative jump destination lower address Given as lower 13 bits. Jump destination address is set as an even byte address.
WPR
: Fixed at 0
15 RN 0
Register number RN Given as 10-bit data. Settable registers are limited.
15 DATA
0
Data Given as 16-bit data.
Rev. 2.0, 09/02, page 314 of 366
GOSUB
: Fixed at 0
15 ABSOLUTE SUBROUTINE ADDRESS H 0
Subroutine upper address Given as upper 10 bits.
15 ABSOLUTE SUBROUTINE ADDRESS L
0
Subroutine lower address Given as lower 13 bits. Subroutine destination address is set as an even byte address.
0
15 Sign extension
Sign
RELATIVE SUBROUTINE ADDRESS H
Relative subroutine destination upper address Given as upper 10 bits. Use sign extension in upper vacant bits.
15 RELATIVE SUBROUTINE ADDRESS L
0
Relative subroutine destination lower address Given as lower 13 bits. Subroutine destination address is set as an even byte address.
NOP3, VBKEM
15 DUMMY 0
Cannot be referred.
15 DUMMY
0
Cannot be referred.
RET, TRAP
Command code words only. No parameters.
Rev. 2.0, 09/02, page 315 of 366
Appendix C Drawing Algorithms
Straight Line Drawing Algorithms: 8-Point Drawing and 4-Point Drawing Figures C.1 (a) and (b) show examples of straight lines plotted on a bit-mapped display. Circles in the figures represent pixels. Due to the characteristics of a bit-mapped display, a straight line is drawn with the pixels arranged in a path differing slightly from an actual straight line. The same line is drawn in figures C.1 (a) and (b), but the algorithms are different, and so the pixel arrangements are also different. In both figures the line starts at the bottom left of the figure and is drawn dot by dot toward the top right corner. With the method shown in figure C.1 (a), the next dot drawn is to the right, or diagonally to the upper right, of the current dot. With the method shown in figure C.1 (b), on the other hand, the next dot drawn is to the right of, or directly above, the current dot. For the sake of convenience, the method in figure C.1 (a) is here called 8-point drawing, and that in figure C.1 (b), 4-point drawing. The difference between 8-point and 4-point drawing is illustrated in figure C.2. With 4-point drawing, the move to draw the next dot can be made in one of only four directions, up, down, left, or right (figure C.2 (b)). With 8-point drawing, moves can also be made in the four diagonal directions (figure C.2 (a)).
(a)
(b)
Figure C.1 Two Representations of a Straight Line on a Raster Display
Rev. 2.0, 09/02, page 316 of 366
(a)
(b)
Figure C.2 Comparison of (a) 8-Point Drawing and (b) 4-Point Drawing Next, 8-point drawing straight line approximation is described, using figure C.3 (a). After pixel A is drawn, either pixel B or pixel C is selected; the basis for selection is proximity to an actual straight line. The same approach is also used in 4-point drawing (figure C.3 (b)). A comparison between 8-point drawing and 4-point drawing shows that closer approximation to a straight line can be achieved with 8-point drawing. However, the algorithm is correspondingly complex, requiring longer processing time.
C B Actual straight line A (a) (b)
Figure C.3 Drawing Dot Determination Process in (a) 8-Point Drawing and (b) 4-Point Drawing
Rev. 2.0, 09/02, page 317 of 366
Readers interested in drawing algorithms can find further information in the sources listed below. 1. Jerry van Aken: "Curve-Drawing Algorithms for Raster Display," ACM Trams. Graph. Vol. 4, No. 2--(April, 1985), 147-169. 2. J.E.Bresenham: "Algorithm for Computer Control of a Digital Plotter," IBM Syst. J. Vol. 4, No. 1 (1965), 25-30 3. J.E.Bresenham: "A Liner Algorithm for Incremental Digital Display of Digital Arcs," Commum. ACM. Vol. 20, No. 2 (February 1977), 100-106 4. P.E.Danielsson "Incremental Curve Generation," IEEE Trans. Comput. Vol. C-19 (September 1970), 783-793 5. W.J.Jr.Bernard: "An Improved Algorithm for the Generation of Nonparametric Curves," IEEE Trans. Comput. Vol. C-22, No. 12 (December 1973), 1052-1060 6. Jerry van Aken: "An Efficient Ellipse--Drawing Algorithm," IEEE Comput. Graph & Appl. Vol. 4, No. 9 (September 1984), 24-35 7. Y.Suenaga: "A High-Speed Algorithm for the Generation of Straight Lines and Circular Arcs," IEEE Trans. Comput. Vol. C-28, No. 10 (October 1979), 728-736
Rev. 2.0, 09/02, page 318 of 366
Appendix D Package Dimensions
26.0 0.2 24 132 133 89 88
Unit: mm
26.0 0.2
176 1 *0.22 0.05 0.20 0.04 44
45
1.70 Max
0.5
0.10 M
*0.17 0.05 0.15 0.04
1.40
1.25
1.0 0 - 8 0.5 0.1
0.10
0.10 0.05
*Dimension including the plating thickness Base material dimension
Hitachi Code JEDEC EIAJ Weight (reference value)
FP-176 -- Conforms 1.9 g
Figure D.1 Package Dimensions (FP-176)
Rev. 2.0, 09/02, page 319 of 366
Appendix E Display Operating Clock and Screen Synthesis
The display operating clock (CLK1) and possible FG screen, BG screen, and video screen display synthesis ranges are shown in tables E.1 to E.8. The following symbols are used in the tables: Table E.1 32-Bit UGM Bus Width, 66 MHz Q2SD Operating Frequency
Screen Synthesis Possibility 320 x 240 480 x 240 640 x 240 640 x 480 800 x 480 CLK1: 6.5 MHz 9.5 MHz 14 MHz 25 MHz 33 MHz O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O X X X X X X X X X O O O X X X X X X X X X
Display Screen Configuration Video FG Screen BG Screen Screen 8 bpp 16 bpp 8 bpp 8 bpp 16 bpp 16 bpp 8 bpp 16 bpp 8 bpp 8 bpp 16 bpp 16 bpp Legend O: Display synthesis possible X: Display synthesis may not be possible \: Display synthesis not possible bpp: Bits per pixel 1. O if there is no video input -- -- 8 bpp 16 bpp 8 bpp 16 bpp -- -- 8 bpp 16 bpp 8 bpp 16 bpp -- -- -- -- -- -- 16 bpp 16 bpp 16 bpp 16 bpp 16 bpp 16 bpp
Note:
Rev. 2.0, 09/02, page 320 of 366
Table E.2
32-Bit UGM Bus Width, 60 MHz Q2SD Operating Frequency
Screen Synthesis Possibility 320 x 240 480 x 240 640 x 480 800 x 480 Video Screen CLK1: 6.5 MHz 9.5 MHz 25 MHz 33 MHz * -- -- -- -- -- -- 16 bpp 16 bpp 16 bpp 16 bpp 16 bpp 16 bpp O O O O O O O O O O O O O O O O O O O O O O O X O O O X X X X X X X X X
Display Screen Configuration FG Screen 8 bpp 16 bpp 8 bpp 8 bpp 16 bpp 16 bpp 8 bpp 16 bpp 8 bpp 8 bpp 16 bpp 16 bpp BG Screen -- -- 8 bpp 16 bpp 8 bpp 16 bpp -- -- 8 bpp 16 bpp 8 bpp 16 bpp
Note: * Not possible since Q2SD operating frequency > twice dot clock. Video input is possible if the Q2SD operating frequency is 64 MHz or higher.
Rev. 2.0, 09/02, page 321 of 366
Table E.3
32-Bit UGM Bus Width, 50 MHz Q2SD Operating Frequency
Screen Synthesis Possibility 320 x 240 480 x 240 640 x 480 800 x 480 Video Screen CLK1: 6.5 MHz 9.5 MHz 25 MHz 33 MHz * -- -- -- -- -- -- 16 bpp 16 bpp 16 bpp 16 bpp 16 bpp 16 bpp O O O O O O O O O O O O O O O O O O O O O X X X O O X X X X X X X X X X
Display Screen Configuration FG Screen 8 bpp 16 bpp 8 bpp 8 bpp 16 bpp 16 bpp 8 bpp 16 bpp 8 bpp 8 bpp 16 bpp 16 bpp BG Screen -- -- 8 bpp 16 bpp 8 bpp 16 bpp -- -- 8 bpp 16 bpp 8 bpp 16 bpp
Note: * Not possible since Q2SD operating frequency > twice dot clock. Video input is possible if the Q2SD operating frequency is 64 MHz or higher.
Rev. 2.0, 09/02, page 322 of 366
Table E.4
32-Bit UGM Bus Width, 40 MHz Q2SD Operating Frequency
Screen Synthesis Possibility 320 x 240 480 x 240 640 x 480 800 x 480 Video Screen CLK1: 6.5 MHz 9.5 MHz 25 MHz * 33 MHz * -- -- -- -- -- -- 16 bpp 16 bpp 16 bpp 16 bpp 16 bpp 16 bpp O O O O O O O O O O O X O O O O O O O O X X X X
Display Screen Configuration FG Screen 8 bpp 16 bpp 8 bpp 8 bpp 16 bpp 16 bpp 8 bpp 16 bpp 8 bpp 8 bpp 16 bpp 16 bpp BG Screen -- -- 8 bpp 16 bpp 8 bpp 16 bpp -- -- 8 bpp 16 bpp 8 bpp 16 bpp
Note: * Not possible since Q2SD operating frequency > twice dot clock. Video input is possible if the Q2SD operating frequency is 64 MHz or higher.
Table E.5
16-Bit UGM Bus Width, 66 MHz Q2SD Operating Frequency
Screen Synthesis Possibility 320 x 240 480 x 240 640 x 480 800 x 480 Video Screen CLK1: 6.5 MHz 9.5 MHz 25 MHz 33 MHz -- -- -- -- -- -- O O O O O O O O O O O O O O O X X X O X X X X X
Display Screen Configuration FG Screen 8 bpp 16 bpp 8 bpp 8 bpp 16 bpp 16 bpp BG Screen -- -- 8 bpp 16 bpp 8 bpp 16 bpp
Rev. 2.0, 09/02, page 323 of 366
Table E.6
16-Bit UGM Bus Width, 60 MHz Q2SD Operating Frequency
Screen Synthesis Possibility 320 x 240 480 x 240 640 x 480 800 x 480 Video Screen CLK1: 6.5 MHz 9.5 MHz 25 MHz 33 MHz * -- -- -- -- -- -- O O O O O O O O O O O O O X X X X X
Display Screen Configuration FG Screen 8 bpp 16 bpp 8 bpp 8 bpp 16 bpp 16 bpp BG Screen -- -- 8 bpp 16 bpp 8 bpp 16 bpp
Note: * Not possible since Q2SD operating frequency > twice dot clock.
Table E.7
16-Bit UGM Bus Width, 50 MHz Q2SD Operating Frequency
Screen Synthesis Possibility 320 x 240 480 x 240 640 x 480 800 x 480 Video Screen CLK1: 6.5 MHz 9.5 MHz 25 MHz 33 MHz -- -- -- -- -- -- O O O O O O O O O O O O O X X X X X
Display Screen Configuration FG Screen 8 bpp 16 bpp 8 bpp 8 bpp 16 bpp 16 bpp BG Screen -- -- 8 bpp 16 bpp 8 bpp 16 bpp
Table E.8
16-Bit UGM Bus Width, 40 MHz Q2SD Operating Frequency
Screen Synthesis Possibility 320 x 240 480 x 240 640 x 480 800 x 480 Video Screen CLK1: 6.5 MHz 9.5 MHz 25 MHz * 33 MHz * -- -- -- -- -- -- O O O O O O O O O O O X
Display Screen Configuration FG Screen 8 bpp 16 bpp 8 bpp 8 bpp 16 bpp 16 bpp BG Screen -- -- 8 bpp 16 bpp 8 bpp 16 bpp
Note: * Not possible since Q2SD operating frequency > twice dot clock.
Rev. 2.0, 09/02, page 324 of 366
Appendix F Example of System Configuration for SuperH
HD64413A, a chip set of SuperH, is designed to facilitate the connection of the SuperH Series CPU. For memory, SDRAM is directly connected. The HD64413A initializes SDRAM mode registers. For a dot clock signal CLK1 for display and the operating clock (MCLK) of HD64413A, a nonsynchronous clock can be used. The display size is determined by the maximum clock frequency that can be input to CLK1. For example, the display size when HD64413A operates under non-interlace mode is roughly 320 x 240 to 480 x 240 dots, and under interlace sink & video mode, it is about 640 x 480 dots. A synthetic display with external video signals can be performed by setting HD64413A to TVsynchronous mode and by supplying HSYNC, VSYNC, ODDF and CKL1 from an external device to HD64413A. Also, a video display can be performed by video-capturing by digitally encoding video signals. Figure F.1 shows an example of the system configuration for the HD64413A. The HD64413A is an application specific IC which is oriented to the realization of a low-cost system for combined display of video, graphics, still picture, and cursor.
Rev. 2.0, 09/02, page 325 of 366
Address SuperH (CPU) Data Rendering clock Display clock CDE SYNC Video encoder Analog in
HD64413A Q2SD
CLK0 CLK1 VIN R,G,B
SELECT
NTSC
Video stream encoder
VQCLK HSYNC VSYNC 320 x 240
Address(14)
Data(32) SDRAM: 16M to 64M UGM
Video
Frame buffer 0
Frame buffer 1 Binary/multivalued source
VCR
Binary work
Display list
Figure F.1 Example of System Configuration Overview
F.1
Determination of Clock
The clocks supplied to HD64413A are clocks input to the CLK1 pin and those input to the CLK0 pin. The clocks input to the CLK1 pin are used as clocks for display control, and the clocks input to the CLK0 pin are used as operating clocks. 1. For the CLK0 pin, the following clock type a or b can be used. a. Method for using clocks output from CKIO pin of SuperH When a SuperH (SH-3, SH-4) operating with 3.3V is used as the CPU, clocks output from the CKIO pin can be used as input clocks for the CLK0 pin. Also, to increase the fan-out of CKIO pin, input the output clock of the CKIO pin to the CLK0 pin of HD64413A via a buffer circuit. b. Method for using clocks other than those output from CKIO pin of CPU
Rev. 2.0, 09/02, page 326 of 366
Clocks of 3.3V level can be used as input clocks for the CLK0 pin. 2. Input clocks for the CLK1 pin must satisfy the following conditions: MCLK [Hz] 2 x CLK1 [Hz] (CLK1 33.3 MHz) MCLK = N x CLK0 (N: either of multiple of 1, 2 or 4)
F.2
Setting of Software Weight
The software weight cycle of SuperH is determined by the relationship of the external bus operating frequency (CKIO) of SuperH and the internal operating frequency (MCLK) of HD64413A. Set the software cycle so that SuperH can detect the :$,7 signal output by HD64413A, taking into consideration the AC timing of both SuperH and HD64413A. Here a case in which CKIO = 20MHz and MCLK = 66MHz are used using SH-3 is described. As shown in figure F.2, by setting the software cycle (Tw) of SuperH to 2, the rule of tWTS and tWTH, which governs the :$,7 pin of SuperH can be observed and the hardware cycle (Twx) between SuperH and HD64413A can be defined. (tWAS1 = 3 tcyc0 + 15 ns (MAX))
T1 CKIO Tw Tw Twx
tWAS1
tWTS
tWTH
Figure F.2 Example of Interface Timing
Rev. 2.0, 09/02, page 327 of 366
F.3
Special Notes on Connection
When connecting SuperH to HD64413A, note the following: 1. When the initial value of &6 pin of SuperH is an input port and signals connected to the &6 and &6 pins of HD64413A are generated from this pin, pull up the &6 pin of SuperH so that the voltage level not to become unstable after canceling hardware reset. 2. When the DMAC built in SuperH is used and the DACK pin is set to active high by initial value setting, connect the inverted signal of DACK pin to the DACK pin of HD64413A by the external circuit. Incidentally, use the DACK pin set to active high, as is. 3. When using SH-4 for SuperH, invert signals output from the :$,7 pin of HD64413A by the external circuit and input them to the 5'< pin of SH-4.
F.4
Initialization Procedures of Address-Mapped Register
Standard procedures of setting initial value to the address-mapped register of HD64413A is described below. Follow the steps 1 to 4. 1. Set SRES = 0, DRES = 1 and DEN = 0 to the system control register and stop the display synchronous operation. Additionally, do not allow access to UGM by SuperH and DMAC after setting these values and before the display synchronous operations start. 2. Set initial values to registers between register addresses H004 to H04A and 056. In particular, depending on the initial values of each bit of H056, initial values are required to be set to the registers related to these bits. 3. When displaying 8-bit/pixel displays or performing cursor display by combining GBM2 to GBM0, set initial values to the color palette register. 4. Set SRES = 0 and DRES = 0 to the system control register and start display synchronous operations. By setting this way, SuperH can make access to UGM. Additionally, to enable the graphics drawn by HD64413A to be checked, normally the DBM of system control register is specified with auto rendering mode or manual display change mode.
Rev. 2.0, 09/02, page 328 of 366
F.5
F.5.1
Memory Assignment
Memory Mapping of HD64413A
The address-mapped registers of HD64413A and UGM are mapped in the cache through space of memory space of SuperH. An example of memory map using a 64-Mbit synchronous RAM as UGM is shown in figure F.3. Also, pins A22 to A1 of HD64413A require the UGM address of HD64413A to be input directly. In this example, A1 to A22 are used as address signals for directly showing the UGM address. For example, when access is made by SuperH to address H000000 of UGM, clear all A22 to A1 pins of HD64413A to 0. In figure F.3, UGM is placed from HA8000000 so that access is made to the cache through space when SuperH makes access to UGM.
Cache through space H'A8000000
Pins MD3 = 1, MD4 = 0
UGM
CS1 space, normal space, cache through area 32 Mbytes
H'A87FFFFF H'A8800000 H'A88002FF
Address-mapped register
16-bit space
Image space of address-mapped register H'A8FFFFFF
Figure F.3 Example of Memory Mapping (Using SH7709)
Rev. 2.0, 09/02, page 329 of 366
F.5.2
Example of Area Placement in UGM
An example of area placement in UGM is shown in figure F.4. This figure shows only an example meaning that other area placement styles are allowed. 1. Frame buffer area (FB0, FB1) Under double-buffer control, these areas are used as a display area (screen coordinates) and drawing area (rendering coordinates). For the display addresses (DSA0, DSA1) of these areas, set the UGM addresses that correspond to every 256-dot position touching Y-axis. 2. Video store area (V0, V1, V2) When using the video capture function, the captured data streams are stored in these areas. The areas are used in order of V0, V1 and V2 each time a synchronous signal is input to the 996 pin. Here the read size is 320 x 240 pixels. For the display addresses of these areas (VSAR0 to VSAR2), set the UGM addresses corresponding to every 16-dot position along Y-axis and every 32-dot position along X-axis, considering that UGM is 16 bit/pixel. Additionally, when the video capture function and video window are not displayed, these areas are not used and are not necessary. 3. Work area (BWAREA) This area is used as a work area. The maximum pixel of X-axis of work coordinates is the pixel quantity specified by the MWX bit of rendering mode register. Accordingly, regardless of the GBM bit of rendering mode register, the memory capacity required as work coordinates is (pixel quantity specified by MWX bit) x (display pixel quantity along Yaxis)/8[Bytes]. For work area addresses (WASH, WASL), set UGM addresses corresponding to every 16-dot position touching Y-axis. Additionally, when the drawing of optional patterns, such as polygons, is not performed, this area is not used and is not necessary. 4. Display list area (DL0, DL1) These areas are used for storing display lists. Either one of DLO and DL1 is used as the read area for HD64413A to fetch display lists, and the other as the write area for SuperH to place display lists. DL0 and DL1 are used alternately by software control. Display list start addresses (DLSAH, DLSAL) can be specified with optional word (16-bit) addresses. 5. Cursor 1, 2 area (CU1, CU2) These areas are used for storing the shape patterns of cursors. For HD64413A, two cursors can be displayed, so each shape is stored respectively in CU1 and CU2. Also, as cursors themselves are displayed as 8-bit/pixel, surely set the display colors of cursors in the color palette.
Rev. 2.0, 09/02, page 330 of 366
Additionally, for both CU1 and CU2, the memory capacity used is 2kB. 6. Display size 640 x 240 dots (the maximum of 640 x 480 dots) 7. Background area (BG) This area is used for a background screen. The start address for this area is specified in screen coordinates.
0 H'000000 0 FB0 256
640
960
1023 dots 12 kbytes 16 dots 12 kbytes 16 dots 12 kbytes 16 dots
H'00D000 CU1 H'015000 H'07D000 V0 CU2
H'0F0000 H'0F8000 H'100000
480 496 512 FB1 768
DL0 DL1
32 kbytes 32 kbytes H'105000 V1 H'17D000 V2
H'1F0000
992 BWAREA 1231 480 kbytes
BG
DL0, DL1: FB0, FB1: BWAREA: CU1: CU2: V0 to V2:
Area for command double-buffer control Area for FG plane Area for work coordinates Area for cursor 1 Area for cursor 2 Area for video buffer
Figure F.4 UGM Memory Map
Rev. 2.0, 09/02, page 331 of 366
F.5.3
Address Seriation in UGM
As shown in figure F.5, when UGM is viewed from SuperH, UGM addresses look as a series of tiles arranged by memory unit. Thus, by using more than one memory units that were not used in area assignment of FB0, FB1, etc., the space can be used as a memory space with a series of addresses. In case of HD64413A, items that can be placed in a memory space with a series of addresses include binary and multi-valued sources and cursor patterns, so normally these are placed in this area. For example, on the right of FB0, a memory space with a series of addresses having (1024-640) pixels x 16 lines = 6114 pixels from the position X = 640, Y = 0, or a capacity of 12 kbytes from the relationship 1 pixel = two bytes, can be secured. Here CU1 assignment or others is performed.
UGM
0th line 16th line 32nd line
Memory unit
32 or 16 pixels
32 or 16 pixels
16 lines
When UGM is viewed from SuperH, UGM addresses turn down within a range of 32x16 pixels (8-bit/pixel) or 16x16 pixels (16-bit/pixel) and go to the top left of the following memory unit.
Figure F.5 UGM Address Transition Overview
Rev. 2.0, 09/02, page 332 of 366
F.6
Special Notes on Data Transfer to UGM
To transfer data such as binary data and display lists by SuperH or the DMA controller to UGM, first do the initial setting to the address-mapped register of HD64413A and start display synchronous operations so as to enable data transfer between SuperH and UGM. Since an access made by SuperH or the DMA controller to UGM may stop data transfer when display synchronous operations are not performed, do not attempt to make access to UGM when display synchronous operations are not performed. Additionally, there is only one bus master that can make access to UGM. Accordingly, when the DMA mode in system control register of HD64413A is normal mode, only SuperH can make access to UGM. Likewise, when the DMA mode is DMA transfer mode, only the DMA controller can make access to UGM. Data transfer is possible even in the midst of drawing processing by HD64413A. When the DMAC built in SuperH is used, surely check TE (transfer end flag bit) and then the DMF flag of status register of HD64413A before finishing DMA transfer.
Rev. 2.0, 09/02, page 333 of 366
Appendix G Example of Display Control
G.1 Determination of Display Size
Display pixels along horizontal direction (Hdot) are required to be values satisfying the following formula. For example, if CLK0 = 33MHz, N = 1, HD = 44.7 /s, Hdot must be 737 pixels or less. Also, the frequency of display dot clock (CLK1) must be CLK1 = Hdot/HD (Hz).
Hdot CLK0 x N = MCLK HD 2 Where, N is a multiple of Q2SD CLK0 is a clock (Hz) input to the CLK0 pin of Q2SD.
HT HD
Hdot
Display area HT > HD cycle (sec) HT: (sec) HD: Display time in Hdot: Quantity of display pixels along horizontal direction (pixel)
Figure G.1 Example of Display Timing
Rev. 2.0, 09/02, page 334 of 366
G.2
Selection of Display Screen
HD64413A has the following three display screens: 1. Foreground screen Displayed at the frontmost. It can be displayed with 8 or 16 bit/pixel and is used mainly for realizing dynamic images in drawing processing. 2. Background screen Displayed at the rearmost. It can be displayed with 8 or 16 bit/pixel and is used mainly for realizing scroll by pixel. 3. Video screen Displayed between the foreground and background screens. It is used for displaying the stream data captured by the video capture function. Each display screen can be selected as the foreground screen by the FBD bit, the background screen by the BG bit, and the video window by the VWE bit.
Rev. 2.0, 09/02, page 335 of 366
G.3
Setting of Synchronous Signal
To enable display control, HD64413A requires synchronous signals to be set in the addressmapped register. An example of register setting of the synchronous signals used for this application note is shown below: 1. Setting example of synchronous signals when the TV synchronous mode is master mode and the scan mode is non-interlace is shown. The display size is 320 x 240 dots. Here, CLK1 = (horizontal display pixel)/(xw time) (Hz).
hc (63.56 s) hsw (4.47 s) xs (9.08 s)
xw (44.7 s)
ys=16 rasters
Effective display range
yw=240 rasters
Figure G.2 Example of Display Timing under Non-interlace Mode
Rev. 2.0, 09/02, page 336 of 366
vsw=3 rasters
vc=262 rasters
Table G.1
Variable hsw xs xw hc
Setting Example of Variables ((TVM1,0) = (0,0), (SCM1,0) = (0,0))
Calculation Formula 4.47 s x CLK1 9.08 s x CLK1 44.7 s x CLK1 63.56 s x CLK1 Value in Display Example 32 65 320 455
CLK1 = 7.159 MHz
Table G.2
Register DSX DSY HDS HDE VDS VDE HSW HC VSP VC
Register Setting Example ((TVM1,0) = (0,0), (SCM1,0) = (0,0))
Calculation Formula (Master Mode) xw yw hsw + xs - 11 hsw + xs - 11 + xw ys - 2 ys - 2 + yw hsw - 1 hc - 1 vc - vsw - 1 vc - 1 Setting Value in Display Example 320 240 68 406 14 254 31 454 258 261
Rev. 2.0, 09/02, page 337 of 366
2. Setting example of synchronous signals when the TV synchronous mode is master mode and the scan mode is interlace & video mode is shown. The display size is 640 x 480 dots. Here, CLK1 = (horizontal display pixel)/(xw time) (Hz).
hc (63.56 s) hsw (4.47 s) xs (9.08 s) ys=16 rasters
xw (44.7 s)
Effective display range (odd-number field)
yw=240 rasters
vsw=3 rasters
vc=262 rasters vc=262 rasters 525 rasters
Effective display range (even-number field)
yw=240 rasters
Figure G.3 Example of Display Timing under Interlace Sink & Video Mode
Rev. 2.0, 09/02, page 338 of 366
vsw=3 rasters
ys=16 rasters
Table G.3
Variable hsw Xs* xw hc
Setting Example of Variables ((TVM1,0) = (0,0), (SCM1,0) = (1,1))
Calculation Formula 4.47 s x CLK1 9.08 s x CLK1 44.7 s x CLK1 63.56 s x CLK1 Value in Display Example 64 131 640 910
CLK1 = 14.318 MHz Note: When using a video encoder, determine xs so that the effective display range does not overlap the color burst.
Table G.4
Register DSX DSY HDS HDE VDS VDE HSW HC VSP VC
Register Setting Example ((TVM1,0) = (0,0), (SCM1,0) = (1,1))
Calculation Formula (Master Mode) xw yw x 2 cycles of hsw + xs - 11 hsw + xs - 11 + xw ys - 2 ys - 2 + yw hsw - 1 hc - 1 vc - vsw - 1 vc - 1 Setting Value in Display Example 640 240 184 824 14 254 63 909 258 261
96<1&
Rev. 2.0, 09/02, page 339 of 366
G.4
G.4.1
Setting and Changing Register Values related to Display Control
Setting of Color Palette
The color palette of HD64413A is designed to write or read color palettes by two-word continuous access. So, when setting values to color palettes, surely set registers containing G and B, following a register containing R. Likewise, when reading values from color palettes, surely read out registers containing G and B, following a register containing R. G.4.2 Switching Procedure of Synchronous Mode
A change in synchronous mode, from master mode to TV synchronous mode and the like, is performed by way of synchronous switching mode. Switching to synchronous switching mode can be performed by setting TVM1 = 0, TVM0 = 1. Also, since HD64413A does not refresh UGM under synchronous switching mode, set DRES = 1, DEN = 0 and switch the mode to one under which HD64413A refreshes UGM, before entering synchronous switching mode. Procedures are shown below. Additionally, as HD64413A refreshes UGM while DRES = 1, DEN = 0 is valid, do not attempt access to UGM by SuperH or DMAC. Switching Procedure to synchronous switching mode: 1. Set BG = 0, VWE = 0, CE1 = 0, CE2 = 0. 2. Set DRES = 1, DEN = 0. Now only refreshing to UGM can be performed. 3. Set TVM1 = 0, TVM0 = 1. HD64413A switches to synchronous switching mode. Returning Procedure from synchronous switching mode: 4. Input a clock to the CLK1 pin. For a switch to TV synchronous mode (TVM1 = 1, TVM0 = 0), also input signals to (;+6<1&, (;96<19 and 2'') pins. 5. To change the display size, setting values to the address-mapped register of HD64413A. 6. By setting TVM1 = 0 and TVM0 = 0, or TVM = 1 and TVM0 = 0, the input clock from the CLK1 pin is effective. Further, set BG = 1, VWE = 1, CE1 = 1, CE2 = 1, as needed. 7. Set DRES = 0, DEN = 1. After internal updating, HD64413A starts displaying.
G.5
Use of Cursor Display
The HD64413A can display two cursors with 32 x 32 pixels placed in the UGM. One cursor has two shape data: cursor blink shape A and cursor blink shape B. They are alternatively displayed
Rev. 2.0, 09/02, page 340 of 366
at the timing specified by BLINKA and BLINKB. Therefore, an area of continuous 2-kbyte addresses per one cursor is required. Using four memory units in the horizontal direction can allocate the continuous 2-kbyte area in the UGM as shown in figure G.4. For details of a single memory unit, see section F.5.3, Address Seriation in UGM.
UGM
Four memory units
Cursor blink shape A
Cursor blink shape B
Cursor area start address
Figure G.4 Cursor Allocation When the HD64413A displays a cursor, a cursor shape data is first read from an address specified by the cursor area start address register. The cursor is painted by referencing the cursor shape data and is displayed.
Rev. 2.0, 09/02, page 341 of 366
Appendix H Example of Drawing Control
H.1 Example of Starting Drawing
HD64413A performs drawing on rendering coordinates and work coordinates based on command groups called display lists. The drawing procedures are shown below: 1. Using SuperH, place LCOFS and SCLIP commands as a display list to UGM. This display list is intended to set initial values of the local offset and system clip ranges of HD64413A. 2. To synchronize the frame change timing and draw start timing, place the VBKEM command following the display list placed in 1 to UGM using SuperH or use the frame change function specified by the DBM bit in the system control register (SYSR). 3. Following the display list placed in 2, place the display list using POLYGON4-series commands and the like to UGM using SuperH to let HD64413A perform drawing. 4. Following the display list placed in 3, place the TRAP command to show the end of display listing. At this moment, the display list preparation is finished. 5. After setting the rendering start address, set 1 to RS bit. By this register setting, you can let HD64413A perform drawing.
H.2
Example of Frame Change by Internal Updating
An example of a frame change by internal updating is described below. In this case, a frame change is performed by internal updating, while fixing the DBM bit at manual display change mode and controlling display start addresses DSA0, DSA1, and RSAR by SuperH. When using the suspend/resume function of drawing, method by which the draw start address and display start address can be controlled is effective. In this case, first the DBF bit in status register should be checked to judge which of DSA0 or DSA1 is the register that determines the display start address. When DBF = 0, DSA0 is the register determining the display start address. Likewise, when DBF = 1, DSA1 is the register determining the display start address. Table H.1 shows the relationship of DBF, DSA0 and DSA1. Table H.1 Relationship of DBF and Display Screen (FG)
DSA0 DBF = 0 DBF = 1 Display screen Drawing screen DSA1 Drawing screen Display screen
As an example, control procedures 1 to 4 of DSA0 and DSA1 of a case DBF = 0 are shown below:
Rev. 2.0, 09/02, page 342 of 366
1. Wait until the internal updating cycle is finished. To confirm the end of internal updating, clear FRM bit and see that the FRM bit becomes 1. 2. Using the WPR command, set in DSA0 the display start address of a position to do displaying in the next internal updating. The display start address set to DSA0 is not reflected as an effective value. This setting value becomes effective only passing an internal updating. 3. Using the WPR command, set 1 to RSAE and the draw start address to RSAR. 4. After transferring display lists, read dummy data from the UGM and then set the RS bit in the system control register to 1 to start drawing. By repeating the steps 1 to 4 above, the display start address set to DSA0 becomes effective by internal updating and frame changing is enabled. The drawing and display timing using the frame change by internal updating are shown in figure H.1:
Rev. 2.0, 09/02, page 343 of 366
DSA0 (Display control)
RSAR (Drawing control)
Processing by Q2SD (1) (2)
Using FRM bit, wait until internal updating is finished Using WPR, set the next display start address (FB0)
Display screen
(3)
Referencing DSA0 by internal updating. (Display FB1)
Using WPR, set the next draw start address (FB0)
(4)
Rev. 2.0, 09/02, page 344 of 366
Display FB1
Using WPR, set the next draw start address (FB0) Using FRM bit, wait until internal updating is finished Using WPR, set the next display start address (FB1) Using WPR, set the next draw start address (FB1)
Drawing
Using WPR, set the next draw start address (FB1)
Drawing Display FB0
Referencing DSA0 by internal updating (Display FB0)
Drawing
Drawing
Figure H.1 Display/Drawing Control Timing Chart (DBF = 0)
Using FRM bit, wait until internal updating is finished
Referencing DSA0 by internal updating (Display FB1)
Display FB1
Using WPR, set the next display start address (FB0)
H.3
H.3.1
Using Example of Draw Commands
Drawing Polygons
Drawing polygons on rendering coordinates using HD64413A can be performed by using work reference, one of rendering attributes, and work coordinates. Drawing procedures by HD64413A are shown below: 1. To clear the work area, execute the CLRW command. 2. Using the FTRAP command, draw on work coordinates the shape of polygon to draw. 3. Using the POLYGON4C command of which the WORK bit with rendering attribute is set to 1, draw a polygon with the shape drawn on the work coordinates. 4. Using the LINE command, draw an outline of the polygon. Practically, the display list to perform the above procedures is generated by SuperH, and drawing is performed by HD64413A based on the display list generated. H.3.2 Drawing Optional Shapes
An optional shape which is a fixed shape with binary pattern having been placed on work coordinates by partially referencing can be drawn. Before placing a binary pattern on work coordinates, the work coordinates must be zero-cleared. To avoid concurrent drawing on work coordinates by SuperH and HD64413A, the zero-clearing of the work coordinates is performed not by the CLRW command but directly by SuperH. H.3.3 Drawing Circles and Ellipses
To draw a circle or an ellipse by HD64413A, the orbit of ellipse is calculated by SuperH, and drawing is performed by the LINE command using the calculated result as parameters. Using Bresenham's circle algorithm, the ellipse orbit is worked out. Drawing a circle is enabled by converting the x, y radiuses of ellipse to same dot quantities. When drawing is required to be performed in a work area, the LINE command should be used. H.3.4 Drawing using Source Data
When using a draw command that references a source by HD64413A, generally it is necessary to judge whether or not source data is stored in UGM on the application software side. In a certain system, the judgment is difficult or processing requires time. As an example to avoid this, there is one method that relates the draw command and the reference position of source by including source data in the display list.
Rev. 2.0, 09/02, page 345 of 366
To embed source data into the display list, place the JUMP command immediately after the draw command so that the source data is skipped as shown in figure H.2. When a multi-valued source is included in the display list, the same method can be applied. In this case, use the POLYGON4A command by setting 1 to the LNi bit with rendering attribute.
Display list Relative branching POLYGON4B JUMP Binary source data
Relative referencing
Next command
Figure H.2 Example of Referencing and Branching H.3.5 Expressing 3D Space
A solid graphics formed with multiple rectangles are rotated by rotating each rectangle. Processing procedures are described below: 1. Define the rectangles that are expressed with 3D coordinates. A set of the rectangles defined with the function forms one solid graphic. 2. Do rotational operation of coordinate values for each rectangle. 3. Determine the order of drawing rectangles. Drawing order is from the depth to the front. First the mean value of Z values of each rectangle is calculated, and the order is set based on the results. In a bubble sorting which is easily described by a source program, sorting is performed by approximately n x n times where the quantity of elements to be sorted is n. In a high-speed sorting method like heap sorting is used, sorting can be finished by approximately n x log n times. 4. Convert 3D coordinate values into 2D coordinate values for each rectangle. Firstly, a position in which the Z value of each vertex exists in the depth of Z-axis is given by the ratio of the position to the Z value. Then, conversion is achieved by multiplying each of four vertices by its ratio. 5. Using the order determined in 3 and the 2D coordinate values obtained in 4, drawing is performed on UGM with the POLYGON4C command as a display list.
Rev. 2.0, 09/02, page 346 of 366
After finishing the above procedures, the display list is generated on UGM, and a 3D space can be expressed by drawing using HD64413A.
H.4
H.4.1
Special Notes on Using Draw Commands
Notes on the Relationship of Local Offset and Current Pointer
Local offset and the current pointer are given their respective values by the order of command execution. So, place commands while taking into consideration the relationship of local offset and the current pointer. The priority order of command placement is shown below. Draw commands having low priority are to be placed first. 1. lcofs command Sets the initial value of local offset. 2. rlcofs command Moves local offset by a relative value to the current local offset. 3. move command Sets the current pointer by adding the current local offset. 4. remove command Moves the current pointer by a relative value to the current pointer currently used. H.4.2 Notes on Using Relative-Series Commands
Commands that control coordinate parameters on relative coordinates are called relative-series commands. When using the relative-series commands, it is necessary to generate a current pointer using the move command and the like beforehand. Also, commands other than relativeseries commands use the current pointer as a register for operation and break it. Therefore, when using relative-series commands performing drawing, do not insert other commands between relative-series commands.
Rev. 2.0, 09/02, page 347 of 366
H.4.3
Notes on Using Source Data
When HD64413A uses the binary and multi-valued sources placed in UGM, source data is taken to the source buffer existing in HD64413A, and drawing is performed using the accumulated source data. The source buffer has a capacity of 16 words, and HD64413A stores every 32-byte data to the source buffer each time the UGM address passes a 16-word border. Because of this, when using binary and mullet-valued sources, it is necessary to let HD64413A perform drawing while taking into consideration to cause source buffer updating. Also, how the source buffer updating is performed is determined by the STYL bit with rendering attribute as described in 1 and 2 below: 1. When STYL with rendering attribute is set to 0 When STYL = 0, consideration must be taken so as to cause source buffer updating when the source capacity is within 32 bytes. The following methods can be considered: a. Specify different source addresses for each command. For example, when referencing binary sources within 32 bytes by the POLYGON4B command, this method can be performed by specifying different addresses for each of POLYGON4B command parameters SOURCE ADDRESSH and SOURCE ADDRESSL. b. Use transparent designation By this method, by preparing binary sources exceeding 32 bytes, only the binary source of a necessary part is drawn when drawing using the draw command of which transparent designation is enabled. 2. When STYL with rendering attribute is set to 1 When STYL = 1, source referencing is performed repeatedly. Accordingly, when a source referencing is finished at an address within 32 bytes, counting from the source reference start address, consideration must be given so as to cause source buffer updating. The following methods can be considered: a. Specify different source addresses for each command. For example, when referencing binary sources within 32 bytes by the POLYGON4B command, this can be performed by specifying different addresses for each of POLYGON4B command parameters SOURCE ADDRESSH and SOURCE ADDRESSL.
Rev. 2.0, 09/02, page 348 of 366
H.5
H.5.1
Functions to Support Drawing Processing
Suspension/Resumption of Drawing
Suspension/resumption of drawing is intended to support drawing functions and is supported from HD64412 (Q2i) on. This function is used when doing drawing processing to the frame buffer (FB) during a background screen (BG) drawing or for forcible interruption with drawing processing. Use of suspension/resumption of drawing is described below. Additionally, the function is available only when 10 is set to the DBM bit of system control register and the double-buffer control is fixed at manual display change. Suspension of Drawing: "Suspension of drawing" is intended to suspend the drawing that is currently being performed. Suspension of drawing can be performed by setting 1 to the RBRK bit of system control register (SYSR). Setting 1 to the RBRK bit by SuperH, HD64413A sets values set to the register inside LSI (current pointer, local offset, clipping range, return address of GOSUB command) to rendering control register 2 at the top of next command that follows after the execution of current draw command is finished, and suspends the drawing. To determine suspension of drawing by SuperH, after setting 1 to the RBRK bit, read out the TRA and BRK bits. If the TRA bit is 1, meaning that drawing is finished by executing the TRAP command, and not suspension by RBRK, do not resume drawing thereafter. If the BRK bit is 1, it means suspension of drawing. Thus, suspension of drawing can be judged by confirming BRK = 1. When the BRK bit becomes 1, read values set to the rendering control register 2, draw start address enable (RSAE) of rendering mode register, draw start address register (RSAR) and the command status register (CSTR) by SuperH software processing, and shelter them on the SuperH memory. Sheltered values are used when resuming the suspended drawing. Thereafter, generate the display list to draw during suspension and execute. Resumption of Drawing: "Resumption of drawing" is intended to resume a drawing suspended by "suspension of drawing". To resume the drawing, place a display list for resuming drawing to UGM using SuperH, start resumption of drawing to the display list (by setting 1 to the RS bit of system control register) and confirm that the RS bit returns to 0. The composition of display list for resuming drawing is described in 1 to 8 below: * Order of display list commands used to resume drawing (1 to 8 in this order) 1. WPR command: Sets the draw start address register values sheltered when suspending drawing to the draw start address register (RSAR). 2. WPR command: Sets the draw start address enable values sheltered when suspending drawing to the start address enable (RSAE).
Rev. 2.0, 09/02, page 349 of 366
3. WPR command: Sets the return address of GOSUB command sheltered when suspending drawing to the return address register (RTNR). 4. UCLIP command: Returns the UCLIP values sheltered when suspending drawing. 5. SCLIP command: Returns the SCLIP values sheltered when suspending drawing. 6. LCOFS command: Returns the local offset values sheltered when suspending drawing. 7. MOVE command: Returns the current pointer values sheltered when suspending drawing. 8. JUMP command: Returns the command status register values sheltered when suspending drawing.
Rev. 2.0, 09/02, page 350 of 366
Appendix I Drawing Performance
Figures I.1 to I.3 show graphs of HD64413A drawing performance. The graphs show the time required for drawing within the range 320 (H) x 240 (V).
(ms) 2.4 2.23
16-bit/pixel drawing
2.2 2.19
FG screen display
2.0
1.81 1.8
Drawing time
1.62 1.6 1.52
FG screen + BG screen display
8-bit/pixel drawing
1.43 1.4 1.38 1.32 1.29 1.2
FG screen display
0.0 320 (H) x 240 (V) 640 (H) x 2480 (V) 800 (H) x 2480 (V)
Display size Conditions * 320 (H) x 240 (V); CLK1 = 7.15 MHz * 640 (H) x 480 (V); CLK1 = 25 MHz * 800 (H) x 480 (V); CLK1 = 33 MHz * MCLK = 66 MHz * Video capture not performed * 32-bit UGM bus width * FG only displayed
Figure I.1 POLYGON4C Drawing Performance when FST = 0 (Drawing Range: 320 (H) x 240 (V))
Rev. 2.0, 09/02, page 351 of 366
(ms) 1.8 1.68
16-bit/pixel drawing
1.6
FG screen display
1.4
1.2
Drawing time
1.0 0.91 0.84 0.78 0.75 0.70 0.68 0.6
FG screen + BG screen display
8-bit/pixel drawing
FG screen display
0.0 320 (H) x 240 (V) 640 (H) x 480 (V) 800 (H) x 480 (V)
Display size Conditions * 320 (H) x 240 (V); CLK1 = 7.15 MHz * 640 (H) x 480 (V); CLK1 = 25 MHz * 800 (H) x 480 (V); CLK1 = 33 MHz * MCLK = 66 MHz * Video capture not performed * 32-bit UGM bus width
Figure I.2 POLYGON4C Drawing Performance when FST = 1 (Drawing Range: 320 (H) x 240 (V))
Rev. 2.0, 09/02, page 352 of 366
(ms) 2.6
2.41 2.4
16-bit/pixel drawing
2.2
FG screen display + video window display + video capture
2.0 1.96
Drawing time
1.8
1.6
1.48 1.4 1.38
FG screen + BG screen display + video window display + video capture FG screen display + video window display + video capture
8-bit/pixel drawing
1.2
0.0 320 (H) x 240 (V) 640 (H) x 480 (V)
Display size Conditions * 320 (H) x 240 (V); CLK1 = 7.15 MHz * 640 (H) x 480 (V); CLK1 = 25 MHz * 800 (H) x 480 (V); CLK1 = 33 MHz * MCLK = 66 MHz * Video window size: 320 (H) x 240 (V) * Video capture size: 320 (H) x 240 (V) * 32-bit UGM bus width
Figure I.3 POLYGON4C Drawing Performance when FST = 0 (Drawing Range: 320 (H) x 240 (V))
Rev. 2.0, 09/02, page 353 of 366
Appendix J Usage of Video Capture Function
J.1
J.1.1
Example of Video Capture Settings
Example of Interlace Composite Capture
* Description Video data with 640 x 480 is captured in interlace mode. Video screen data with 640 x 480 is displayed on the full-size screen. * Q2SD register setting Video decoder initialization: Interlace output 640 x 480 mode MEMR DSMR REMR DSX DSY DSA0R DSA1R DSMR2 HVPR VVPR VSAH0 VSAL0 VSAH1 VSAL1 VSAH2 VSAL2 VSIZEX VSIZEY VIMR : H0031 (64 Mbits x 32 bits x 1) : H0003 (non-interlace, master mode, refresh 3) : H0040 (BG: OFF, FG/BG: 8 bits, 1024 mode) : H0280 (640) : H01E0 (480) : H0000 (B0000000) : H0008 (B0080000) : H0409 (video display ON, cursor1 display OFF, cursor2 display OFF, FG display OFF, YC RGB conversion ON) : H0000 (X coordinate 0) : H0000 (Y coordinate 0) : H0018 (B0180000) : H0000 : H0028 (B0280000) : H0000 : H0038 (B0380000) : H0000 : H0280 (640) : H01E0 (480) : H0005 (YC RGB conversion OFF, interlace composite capture, horizontal reduction ratio 1, vertical reduction ratio 1)
Rev. 2.0, 09/02, page 354 of 366
0
640 FG0
1023 480 480
800000 100000
FG1 Display list
280000 380000 480000
Video 1 Video 2 Video 3
480 480 480
7FFFFF
Memory map
640
Figure J.1 Interlace Composite Capture J.1.2 Example of Modifying Video Data Size
* Description Video data with 640 x 480 is captured. Both the horizontal and vertical reduction ratios are specified to 1/4 and the video display positions are shifted by 80 in the X and Y direction. The video screen data with 160 x 120 is displayed on the screen with 320 x 240. * Q2SD register setting BT initialization program: Monitor command WW (video display size 640 x 480 mode) MEMR DSMR REMR DSX : H0011 (16 Mbits x 16 bits x 2) : H0003 (non-interlace, master mode, refresh 3) : H0400 (BG: ON, FG/BG: 8 bits, 512 mode) : H0140 (320)
Rev. 2.0, 09/02, page 355 of 366
480
DSY DSA0R DSA1R DSMR2 HVPR VVPR VSAH0 VSAL0 VSAH1 VSAL1 VSAH2 VSAL2 VSIZEX VSIZEY VIMR
: H00F0 (240) : H0000 (B0000000) : H0002 (B0020000) : H0409 (video display ON, cursor 1 display OFF, cursor 2 display OFF, FG display OFF, YC RGB conversion ON) : H0050 (X coordinate 80) : H0050 (Y coordinate 80) : H0008 (B0080000) : H0000 : H0008 (B0100000) : H0000 : H0018 (B0180000) : H0000 : H00A0 (160) : H0078 (120) : H0385 (YC RGB conversion OFF, interlace composite capture, horizontal reduction ratio 1/4, vertical reduction ratio 1/4)
Rev. 2.0, 09/02, page 356 of 366
0 1F3FF 3F3FF FG0 FG1
320
512 240 240
80000 100000 180000
Video 1 Video 2 Video 3
240 240 240
Display list
Figure J.2 Interlace Composite Capture (Horizontal and Vertical Reduction Ratios = 1/4)
,,,,,, ,,, ,,,,,, ,,, ,,,,,, ,,,,,, ,,, ,,,,,, ,,,, ,,,, ,,,,
37FFFE Memory map 640
480
Video decoder output
Video decoder output
Horizontal reducation ratio: 1/4
320
80
160
240
120
Display screen
Rev. 2.0, 09/02, page 357 of 366
J.2
J.2.1
Example of Usage of Captured Data
When Displaying Captured Data on Realtime Video Screen
When the VIE bit in VIMR is set to 1 and the VWE bit in DSMR2 is set to 1, the latest video stream data stored in the video storage area is displayed realtime. In this case, either of the following settings must be made. * When the RGB bit in VMIR is 1, clear the VWRY in DSMR2 to 0. * When the RGB bit in VMIR is 0, set the VWRY in DSMR2 to 1. J.2.2 When Handling Captured Data as Multi-Valued Source Data
When VIE = 0 is set and video capturing is stopped, the video storage area where the latest video stream data is stored in the VID1,0 bits of VIMR is shown. If video capture function is executed when the RGB bit in VMIR is 1, it is possible to reference the video storage area specified by VID1,0 as a 16-bit/pixel multi-valued source. Additionally, VID1,0 has no meaning while video capturing is going on (VIE = 1). To reference VID1,0, first stop video capturing (VIE = 0). * Description Video captured data is converted into RGB format and stored in the BG screen. At this time, the video captured data as multi-valued source is mapped onto figures and is drawn using drawing function. * Q2SD register setting BT initialization program: Monitor command WW (video display size 640 x 480 mode) MEMR DSMR REMR DSX DSY DSA0R DSA1R BGSX BGSY DSMR2 HVPR VVPR : H0010 (16 Mbits x 16 nits x 2) : H0405 (Non-interlace, master mode, refresh 5, BG: ON) : H0001 (FG/BG: 16 bits, 512 mode) : H0140 (320) : H00F0 (240) : H0000 (B0000000) : H0004 (B0040000) : H0000 (0) : H0200 (512) : H0001 (video display ON, cursor 1 display OFF, cursor 2 display OFF, FG display ON, YC RGB conversion OFF) : H00A0 (X coordinate 160) : H0078 (Y coordinate 120)
Rev. 2.0, 09/02, page 358 of 366
VSAH0 VSAL0 VSAH1 VSAL1 VSAH2 VSAL2 VSIZEX VSIZEY VIMR
: H0008 (B0080000) : H0000 : H0008 (B0081400) : H1400 : H0009 (B009C100) : HC100 : H00A0 (160) : H0078 (120) : H0183 (YC RGB conversion ON, Non-interlace capture, horizontal reduction ratio 1/4, vertical reduction ratio 1/4)
0 1F3FF FG0 320 240 512
320 40000 FG1 80000 240 0 240 2 100000 110000 Display list 0 Display list 1 Video 1 BG 240
37FFFE Memory Map
240
,,, ,,, ,,,
320 BG BG Display screen
BG Data captured on the FG is rotated and activated.
Figure J.3 Example of Video Data Usage
Rev. 2.0, 09/02, page 359 of 366
Start
CLK0 exceeds 64 MHz?
No
Reconfigure system. CLK0 must exceed 64 MHz.
Yes
CLK1 exceeds 64 MHz?
Yes
Reconfigure system. Modify size and configuration (8/16) for display screen.
No
Bus width of UGM is 32 bits?
No
Reconfigure system. Memory must be X32 product.
Yes
Display mode is non-interlace?
Yes
A
No
Display mode is interlace sync?
Yes
B
No
Display monitor is interlace type? Non-interlace Screen size is correct? Interlace
Data correctly composed?
No
Invert ODEV in DSMR
No Yes
Modify screen size
Yes
Blurring on screen?
No
Video capture mode is non-interlace?
Yes
Yes
Reconfigure system. Modify display method.
No
Video capture mode is non-interlace (even- or odd-only)?
Yes
Something wrong with displayed video screen?
No
Blurring on displayed video screen?
No
No
Yes
Reconfigure system. Modify display method.
Yes
Use external video decoder signals to perform external TV sync End
Figure J.4 Q2SD Video Setting Flow (1)
Rev. 2.0, 09/02, page 360 of 366
A
Display monitor is interlace type?
Interlace
Non-interlace
Blurring on screen?
Yes
Reconfigure system. Modify display method.
No
Video capture mode is non-interlace?
Yes
No
Screen size is correct?
Yes
No
Modify screen size
End
Figure J.5 Q2SD Video Setting Flow (2)
Rev. 2.0, 09/02, page 361 of 366
B
Display monitor is interlace type? Non-interlace
Interlace
Blurring on screen?
Yes
Reconfigure system. Modify display method.
No
Video capture mode is non-interlace?
Yes
No
Something wrong with displayed video screen?
Yes
Reconfigure system. Modify display method.
Video capture mode is interlace composite? No
Yes
Screen size is correct? No
Yes
Modify screen size
End
Figure J.6 Q2SD Video Setting Flow (3)
Rev. 2.0, 09/02, page 362 of 366
J.3
J.3.1
Video Decoder
Field Control by Video Decoder
Q2SD 66 MHz CLK0 VHS VVS VODD VQCLK 8 VIN7 to VIN0
NTSC video decoder HRESET VRESET FIELD QCLK VD15 to VD8 VD7 to VD0 YIN
10 F Vin 75
16
SDA SCL OE
32 28.63 MHz SDRAM 8 I2C driver SDRAM SCL SDA CPU-bus 5V/3.3V PCA9515 +5 V +3.3 V
Figure J.7 Example of Connection of Video Capture Circuit Since the video decoder in this figure is a mixed-analog-digital device with a 5-V power-supply 2 and a 3.3-V digital interface, the I C interface requires conversion from 5 V to 3.3V. The Q2SD and video decoder are only connected by the eight data lines (VIN0 to VIN7), syncsignal lines (VHS and VVS), sync-clock line (VQCLK), and field-signal line (VODD). The I C driver connected to the video decoder via the PCA9515 is used to set the video decoder by the CPU. The combination of fields in interlacing by the Q2SD can be switched to match the source. Since the combination of fields (top and bottom fields) is not explicitly stipulated in the NTSC specification, two combinations are possible. Most video decoders, therefore, include a polarityinversion function for the FIELD signal.
2
Rev. 2.0, 09/02, page 363 of 366
Frame Top Bottom Format
1 1 2
2 3 4
3 5 6
4 7 8
1 2 1
2 4 3
3 6 5 Bottom first
4 8 7
Top first (TV, DVD)
An example of the timing of the output of data in the interlaced operation of an NTSC video decoder is shown in figure J.8. For most video decoders, the timing of the transitions of the FIELD signal in interlaced operation differs between the odd and even fields.
VRESET HRESET FILD (Odd) FILD (Even) CLK x 2 ACTIVE QCLK 1H 2H
VD[15:8]
,,,,,,,,,, ,
Figure J.8 Example of Interlaced Data Output Timing for Decoder
J.3.2
Video Decoder Settings
The Q2SD's video-input function should be configured to operate with a video decoder which outputs data in the 8-bit streaming video format prescribed in ITU-601. The operation of the following decoders has been examined at our company: the Bt815A, Bt817A, Bt819A, Bt827A/B, Bt829A/B, and Bt835. All of these decoders are manufactured by Rockwell. When the video decoder is connected to the Q2SD, the video decoder is controlled via the I2C interface. The video decoder thus must be initialized by the CPU via the I2C interface or I2C driver before the video data is captured. The following settings are needed. * * * * * Data output format : Any mode of NTSC Data size : VGA/QVGA/Any Output format : Interlaced/non-interlaced Interface : 8-bit video stream Contrast : Any
Rev. 2.0, 09/02, page 364 of 366
* Luminance * Hue : Any
: Any
The data size should be specified as the maximum size except where the reduction size for video capture cannot be specified. However, when the size in the Y direction is specified in the video decoder, an external circuit in which the VHS and VQCLK signals are not output on the invalid line may be required. Contrast, luminance, and hue values for the sequence of images to be captured should be specified to registers in the video decoder.
Rev. 2.0, 09/02, page 365 of 366
Appendix K Product Lineup
Operating Temperature HD64413ASF Regular specification products Wide-range specification products High reliability products for automobile application 0C to +70C Electrical Characteristics Shown in section 7 Reliability Standard
HD64413ASFI
-40C to +85C
Shown in section 7 Ta = -40C to +85C
Standard
HD64413ASFD
-40C to +85C
Shown in section 7 Ta = -40C to +85C
High reliability
Rev. 2.0, 09/02, page 366 of 366
HD64413A Q2SD User's Manual
Publication Date: 1st Edition, October 1999 2nd Edition, September 2002 Published by: Business Operation Division Semiconductor & Integrated Circuits Hitachi, Ltd. Edited by: Technical Documentation Group Hitachi Kodaira Semiconductor Co., Ltd. Copyright (c) Hitachi, Ltd., 1999. All rights reserved. Printed in Japan.

▲Up To Search▲

Price & Availability of HD64413A

	To Download HD64413A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .